Edge-Optimized DFT Lead for SoCs

EnCharge AI; United States; On-site; USD 200,000 - 250,000; Full time

Job summary

EnCharge AI in the United States is seeking a Design for Test (DFT) Lead to architect end-to-end DFT for complex SoCs, including Boundary Scan and MBIST, with focus on testability for edge-to-cloud hardware.

You will drive IST and POST strategies for in-systems health, oversee ATPG and scan insertion, and partner with Design, Physical Design, and Yield teams to balance coverage with area and power.

Qualifications

• 12+ years in DFT with leadership experience
• Bachelor’s degree in a related field
• Expertise with MBIST and boundary scan technologies
• Experience with ATPG for stuck-at, path delay, transitions
• Proficiency with MBIST repair and IJTAG (IEEE 1687)
• Experience with FinFET nodes (7nm+)
• Experience in low-power DFT for multi-voltage designs

Responsibilities

• Architect end-to-end DFT architecture for complex SoCs, including Boundary Scan and MBIST
• Develop IST and POST strategies for edge data centers
• Oversee scan insertion and ATPG (stuck-at, transition, path delay)
• Lead Memory/Logic BIST initiatives and repair capabilities
• Collaborate with Design, Physical Design, Yield to balance coverage vs. area/power
• Lead post-silicon bring-up and debug on ATE to minimize test time

Skills

DFT leadership

MBIST

Boundary Scan

IJTAG

ATPG

Memory/Logic Test

Power-aware testing

Edge data-center test

Education

Bachelor’s degree in a related field

Tools

Synopsys TestMAX

Mentor Tessent

Cadence Modus

Job description

EnCharge AI in the United States is seeking a Design for Test (DFT) Lead to architect end-to-end DFT for complex SoCs, including Boundary Scan and MBIST, with focus on testability for edge-to-cloud hardware.

You will drive IST and POST strategies for in-systems health, oversee ATPG and scan insertion, and partner with Design, Physical Design, and Yield teams to balance coverage with area and power.