DFT Engineer

Quest Global; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Quest Global in San Jose, CA seeks an experienced DFT Engineer to drive testability for advanced SoCs. You will design and implement DFT architectures, insert scan chains, MBIST, TAP controllers, and integrate with synthesis and verification flows. The ideal candidate has a Bachelor's in EE/CE/CS, 7+ years in DFT, and hands-on experience with ATE, JTAG, MBIST, and related tools.

Master’s or PhD is a plus. Location: San Jose, CA.

Qualifications

• Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 7+ years of experience in DFT architecture, implementation, ATPG, and verification for SoCs.
• Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).
• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.

Responsibilities

• Complete all Test Design Rule Checks and Design changes to fix TDRC violations to achieve high test quality.
• Insert DFT logic, including scan chains, MBIST, TAP controller, Clock Control block, and other DFT IP blocks.
• Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic and connect to core and TAP interfaces.
• Design Verification of DFT logic and test pattern generation.
• Design and Implement System Level Test strategy.

Skills

DFT architecture

ATPG

SoC verification

Test methodologies (ATEMBISTJTAGSLT)

Education

Bachelor's degree in EE/CE/CS or related field

Master's degree or PhD in Electrical Engineering/Computer Engineering/CS or related field

Tools

Synopsys Design Compiler

Synopsys DFT Max

Siemens EDA Tessent

TestKompress

Job description

Quest Global is hiring for an experienced engineer for DFT Engineer job position. Below is the job ask ::

Location: San Jose,CA

• Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.


• 7+ years of experience in DFT architecture, implementation, ATPG, and verification for SoCs.


• Experience with industry-standard test methodologies and platforms, such as (but not limited to) ATE, MBIST, JTAG, or System Level Test (SLT).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.


• Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.


• Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).


• Experience with silicon process and technology nodes for high speed and low power consumption.


• Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).

Responsibilities:

• Complete all Test Design Rule Checks and Design changes to fix TDRC violations to achieve high test quality.


• Insert DFT logic, including scan chains, MBIST, TAP controller, Clock Control block, and other DFT IP blocks.


• Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic and connect to core and TAP interfaces.


• Design Verification of DFT logic and test pattern generation.


• Design and Implement System Level Test strategy.