Principal Silicon Integration Engineer - PCIe/CXL

Astera Labs; San Jose, Northern (CA, KY); Hybrid; USD 133,000 - 185,000; Full time

Benefits offered by this job

Health insurance

Job summary

Astera Labs is hiring a Principal Software Integration Engineer to help build and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.

This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of digital design experience, including at least one full chip from spec to tapeout.
• Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
• Hands-on timing closure, CDC, lint, and low-power design techniques.
• Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration.

Responsibilities

• RTL design for assigned blocks from microarchitecture through synthesis sign-off.
• Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
• Drive design reviews, lint, CDC, and timing closure to silicon-ready quality.
• Mentor junior engineers and contribute to design methodology.
• Debug pre-silicon and post-silicon issues across RTL, gate-level, and emulation.

Skills

Verilog/SystemVerilog

RTL coding

Synthesis flows

Timing closure

CDC

Lint

Low-power design techniques

High-speed interfaces knowledge

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

MS or PhD in Electrical Engineering or Computer Engineering

Tools

Synthesis tools

EDA tools

DFT tooling

Job description

Astera Labs is hiring a Principal Software Integration Engineer to help build and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.

This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take