Senior AI-Driven RTL Design & Formal Verification Engineer

Astera Labs; San Jose (CA); On-site; USD 161,000 - 200,000; Full time

Job summary

Astera Labs in San Jose is seeking a Senior Software Engineer for AI-enabled RTL design and formal verification. You will build and deploy AI-driven agents to accelerate RTL and physical design, static analysis, and verification workflows.

You will develop agentic AI solutions, integrate them with CAD/EDA flows, and create design databases and dashboards to surface engineering data for faster design closure. Collaboration with RTL, DV, and CAD/EDA teams is essential.

Qualifications

• Bachelor's or master's in EE/CS or equivalent experience.
• 4–10 years of software engineering with RTL/verification exposure.
• Proficiency in Python for rapid prototyping.
• Experience with LLMs and multi-agent systems.
• Familiarity with Verilog/SystemVerilog and formal verification tools.

Responsibilities

• Design and deploy AI apps using LLMs and agentic frameworks for RTL/verification.
• Build infra to deploy AI assistants and multi-turn dialogues for designers and engineers.
• Develop agentic AI solutions for RTL linting, RTL optimization, bug triage, formal proof convergence.
• Integrate solutions with CAD/EDA flows.
• Create design databases and dashboards to surface engineering data.
• Collaborate with RTL, DV, formal verification, and CAD/EDA teams.

Skills

Python

RTL design

Formal verification

LLMs / AI for CAD

Data structures & algorithms

Communication skills

Education

Bachelor's or Master's in EE/CS

Tools

Verilog/SystemVerilog

JasperGold / VC Formal

Job description

Astera Labs in San Jose is seeking a Senior Software Engineer for AI-enabled RTL design and formal verification. You will build and deploy AI-driven agents to accelerate RTL and physical design, static analysis, and verification workflows.

You will develop agentic AI solutions, integrate them with CAD/EDA flows, and create design databases and dashboards to surface engineering data for faster design closure. Collaboration with RTL, DV, and CAD/EDA teams is essential.