Digital Synthesis & Timing Engineer — ASICs

Qualcomm; San Diego (CA); On-site; USD 98,500 - 147,700; Full time

Benefits offered by this job

RSU grants

Annual discretionary bonus

Competitive benefits

Job summary

Qualcomm Technologies, Inc. in San Diego seeks an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP development for high‑performance, low‑power SoCs. You will work with cross‑functional groups to determine product execution paths.

The role emphasizes digital synthesis, STA, scripting, and precise timing closure across teams to deliver robust, production‑ready IP.

Qualifications

• Bachelor’s degree in Science, Engineering, or related field.
• Bachelor/Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 0–1+ years hardware engineering experience or related work.

Responsibilities

• Perform digital synthesis and static timing analysis for complex digital designs.
• Collaborate with design, verification and PD teams to ensure timing closure and design optimization.
• Analyze and resolve timing issues with cross-functional teams.

Skills

EDA tools

Timing analysis

Scripting (Python/TCL)

Digital/VLSI design basics

Education

Bachelor’s degree in Science/Engineering

Bachelor/Master’s in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Cadence Genus

Job description

Qualcomm Technologies, Inc. in San Diego seeks an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP development for high‑performance, low‑power SoCs. You will work with cross‑functional groups to determine product execution paths.

The role emphasizes digital synthesis, STA, scripting, and precise timing closure across teams to deliver robust, production‑ready IP.