Senior ASIC STA Engineer - On-Site San Jose

eInfochips (An Arrow Company); San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

401k with matching

Disability insurance

HSA/HRA options

Tuition reimbursement

Job summary

eInfochips, an Arrow company, seeks an experienced ASIC STA engineer to lead timing closure across block, sub-chip, and full-chip levels on-site in San Jose, CA. You will perform timing checks and manage ECO tasks, while contributing to extraction and STA flow development and convergence strategies.

Bachelor's degree required; 8+ years in ASIC STA; 5+ years digital IC design with Synopsys EDA tools; strong problem-solving and communication abilities; proficient in Windows/Linux and MS Office;

Qualifications

• Degree in Electrical Engineering or Computer Engineering
• 8 years of ASIC STA (Static Timing Analysis) experience
• 5 or more years of experience with digital IC design using Synopsys EDA tools
• Strong technical problem-solving skills
• Windows OS and LINUX OS and Microsoft office suite tools proficiency
• Effective and clear communication skills and good ability to work with others
• Work accurately with excellent attention to detail
• Ability to work simultaneously on multiple projects and follow up on responsibilities
• Self-starter who requires minimal oversight
• Experience with Siemens Physical Verification tools and methods
• Radiation effects analysis knowledge/experience
• Advanced node and SOI CMOS technology design experience

Responsibilities

• Closing timing at block, sub-chip, and full-chip levels with quality checks (setup, hold, transition, noise) and ECO task management
• Extraction and STA flow development, convergence strategies

Skills

8+ years ASIC STA

Synopsys EDA tools

problem solving

communication

attention to detail

multi-project handling

self-starter

Education

Bachelor's Degree in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Cadence Tempus

Primetime/PTPX/Tweaker

Job description

eInfochips, an Arrow company, seeks an experienced ASIC STA engineer to lead timing closure across block, sub-chip, and full-chip levels on-site in San Jose, CA. You will perform timing checks and manage ECO tasks, while contributing to extraction and STA flow development and convergence strategies.

Bachelor's degree required; 8+ years in ASIC STA; 5+ years digital IC design with Synopsys EDA tools; strong problem-solving and communication abilities; proficient in Windows/Linux and MS Office;