Senior ASIC STA & Timing Closure Engineer

Broadcom Inc.; San Jose (CA); On-site; USD 143,800 - 230,000; Full time

Benefits offered by this job

Annual bonus

Equity grants

Health/dental/vision insurance

401(k) with match

ESPP

Job summary

Broadcom Inc. in San Jose, CA seeks an experienced Full Chip STA Engineer to ensure ASIC meets performance targets across PVT corners and operating modes. You will own timing closure, author SDCs, and collaborate with RTL, PD and DFT teams to balance power and performance.

The role requires extensive scripting (Tcl/Python/Perl/Shell) and a track record of driving timing closures with Cadence or Synopsys tools. Expect a competitive compensation package and strong engineering teamwork.

Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering.
• 12+ years hands-on experience in ASIC STA and timing constraints development.
• Experience with Cadence or Synopsys tools for timing closure.
• Proven ability to drive timing closure by managing on‑chip variation derates and optimizing multi‑mode multi‑corner constraints.

Responsibilities

• Own the final timing closure for ASIC, performing quality checks across all PVT corners.
• Author, validate, and maintain SDC for various modes including functional and test modes (Scan, MBIST, ATPG).
• Analyze foundry guidelines and incorporate sign‑off corners, margins, and derates into timing analysis flows and methodologies.
• Apply advanced timing concepts: On‑Chip Variation (AOCV/POCV), Crosstalk, and IR‑drop aware STA.
• Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environments.
• Automate, generate, and implement ECOs to fix setup, hold, and transition violations in the design cycle.
• Write and maintain high‑level scripts in Tcl, Python, and Perl to automate analysis flows and data mining.
• Collaborate with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard‑banding requirements.
• Analyze trade‑offs between power, performance, and area to drive decisions into overall chip implementation flows.
• Document best practices and lessons learned to drive continuous improvements in future projects.

Skills

Tcl scripting

Python scripting

Perl scripting

Shell scripting

Problem solving

Team player

Communication skills

ASIC timing analysis

Cadence tools

Synopsys tools

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Tools

Cadence tools

Synopsys tools

Job description

Broadcom Inc. in San Jose, CA seeks an experienced Full Chip STA Engineer to ensure ASIC meets performance targets across PVT corners and operating modes. You will own timing closure, author SDCs, and collaborate with RTL, PD and DFT teams to balance power and performance.

The role requires extensive scripting (Tcl/Python/Perl/Shell) and a track record of driving timing closures with Cadence or Synopsys tools. Expect a competitive compensation package and strong engineering teamwork.