Senior ASIC Synthesis & Timing Lead

Positron AI; United States; On-site; USD 195,000 - 275,000; Full time

Benefits offered by this job

Health insurance

Life and disability coverage

Hospital coverage

Unlimited PTO

13 paid holidays

Remote-first culture

Company-provided equipment

Job summary

Positron AI in the United States seeks a Principal Mid-End ASIC Engineer to own synthesis, timing convergence, and implementation readiness across our AI accelerator roadmap. This hands-on role turns RTL into production-ready netlists while coordinating with architecture, RTL, and backend teams.

You will shape synthesis methodologies, create constraints, and drive physical-aware optimization using Cadence Genus and Design Compiler, with Tcl and Python scripting.

Qualifications

• 12+ years of ASIC implementation experience with tapeouts.
• Expert in synthesis methodology and flow development.
• Strong RTL design principles and implementation-friendly coding.

Responsibilities

• Define and own synthesis methodology across ASIC generations.
• Own hands-on synthesis and constraint development with QoR improvements.
• Drive timing closure and manage physical-aware optimization.
• Collaborate with architecture/RTL and backend teams to mitigate timing risks.
• Lead AI-enabled engineering to improve timing analysis and automation.

Skills

Synthesis methodologies

Timing convergence

RTL design principles

Scripting: Tcl/Python

Cadence Genus

Synopsys Design Compiler

SDC constraints

5nm+ process knowledge

Debugging/root-cause analysis

QoR optimization

Tools

Cadence Genus

Synopsys Design Compiler

Job description

Positron AI in the United States seeks a Principal Mid-End ASIC Engineer to own synthesis, timing convergence, and implementation readiness across our AI accelerator roadmap. This hands-on role turns RTL into production-ready netlists while coordinating with architecture, RTL, and backend teams.

You will shape synthesis methodologies, create constraints, and drive physical-aware optimization using Cadence Genus and Design Compiler, with Tcl and Python scripting.