Staff ASIC Synthesis & Timing Engineer

Chiparama; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Chiparama in San Jose, California, is seeking a member for the ASIC Implementation team. You will lead the synthesis and timing of complex designs, interfacing with various internal and external teams to ensure quality delivery.

The ideal candidate will have a minimum of 15 years of experience in electrical engineering with extensive knowledge of frontend tools and multiple tapeouts. Join us to work on exciting consumer electronics!

Qualifications

• 15+ years of experience in semiconductor ASIC implementation.
• Experience with multiple tapeouts and frontend tools.
• Strong knowledge of timing closure and scripting.

Responsibilities

• Lead synthesis and timing of complex designs.
• Develop constraints for full chip and block.
• Interface with design and library teams.

Skills

Synthesis and Timing

TCL scripting

Frontend tools (Primetime, DC, VCLP)

Education

BS in Electrical Engineering with 15 years experience or MS with 12 years experience

Job description

Overview

As a member of the ASIC Implementation team, you will be part of the team implementing new technologies in a variety of exciting consumer electronic devices. You will be directly involved in:

• Leading a Synthesis and Timing of complex designs, provide guidance, interface with RTL team for quality RTL delivery
• Full chip and Block constraints development and constraints generation.
• Full chip and Block Synthesis, STA and timing closure
• Interfacing with internal external teams including Design, IP, Library
• Methodology & Flow development of Synthesis, Formality, STA, Low power checks & Timing Closure
• Working independently with the PNR & RTL design team on Physical implementation and Power-intent requirements

Qualifications

• BS+ 15 or MS+ 12 Years in E.E
• Should have done multiple Tapeouts, have extensive experience in frontend tools such as Primetime, DC, VCLP, Formality, UPF, LEC, Timing closure and timing
• Extensive knowledge of PT/DC is important. Good in TCL scripting.