Senior ASIC Timing & STA Engineer

Apple Inc.; Melbourne (KY); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Kentucky seeks an ASIC STA Engineer responsible for timing sign-off, STA and sign-off flow development, and ownership of IP and block timing constraints from synthesis through to sign-off to ensure timing quality.

You will work with RTL, CAD and Physical teams to close timing, develop new timing constraints and improve flows. The ideal candidate has a BS in a technical discipline with 10+ years of ASIC experience, strong scripting skills (Tcl/Perl), and proven timing closure

Qualifications

• BS degree in technical discipline with minimum 10 years of relevant experience.
• Experience with ASIC timing closure flow and methodology.
• Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, variations and signal integrity issues.
• Hands on experience in timing/SDC constraints generation and management.
• Proficient in scripting languages (Tcl and Perl).
• Familiarity with synthesis, DFT and backend related methodology and tools.
• Strong communication skills are a pre-requisite - you will collaborate with many diverse groups at Apple.
• The ideal candidate will be a self-starter and highly motivated to be successful at Apple.

Responsibilities

• Timing sign-off, STA and sign-off flow development.
• Ownership of IP and block level timing constraints from synthesis to sign-off.
• Work with RTL designer to understand design intent and clock structure, with CAD to develop flow, and with Physical design to close/ sign-off timing.
• Develop ideas to verify timing constraints and improve flows.

Skills

Timing constraints

Primetime STA

Tcl scripting

Perl scripting

Communication skills

Education

BS degree in technical discipline

Tools

Primetime

Job description

Apple Inc. in Kentucky seeks an ASIC STA Engineer responsible for timing sign-off, STA and sign-off flow development, and ownership of IP and block timing constraints from synthesis through to sign-off to ensure timing quality.

You will work with RTL, CAD and Physical teams to close timing, develop new timing constraints and improve flows. The ideal candidate has a BS in a technical discipline with 10+ years of ASIC experience, strong scripting skills (Tcl/Perl), and proven timing closure