Lead ASIC Synthesis & Timing Engineer

Chiparama; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Chiparama in San Jose, California, is seeking a member for the ASIC Implementation team. You will lead the synthesis and timing of complex designs, interfacing with various internal and external teams to ensure quality delivery.

The ideal candidate will have a minimum of 15 years of experience in electrical engineering with extensive knowledge of frontend tools and multiple tapeouts. Join us to work on exciting consumer electronics!

Qualifications

• 15+ years of experience in semiconductor ASIC implementation.
• Experience with multiple tapeouts and frontend tools.
• Strong knowledge of timing closure and scripting.

Responsibilities

• Lead synthesis and timing of complex designs.
• Develop constraints for full chip and block.
• Interface with design and library teams.

Skills

Synthesis and Timing

TCL scripting

Frontend tools (Primetime, DC, VCLP)

Education

BS in Electrical Engineering with 15 years experience or MS with 12 years experience

Job description

Chiparama in San Jose, California, is seeking a member for the ASIC Implementation team. You will lead the synthesis and timing of complex designs, interfacing with various internal and external teams to ensure quality delivery.

The ideal candidate will have a minimum of 15 years of experience in electrical engineering with extensive knowledge of frontend tools and multiple tapeouts. Join us to work on exciting consumer electronics!