Synthesis & STA Engineer

I2Intech LLC; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

I2Intech LLC is seeking a Synthesis & STA Engineer to own timing constraints from RTL through post-route across corners and modes in San Jose, CA. You will develop constraints, run synthesis with Design Compiler/Genus and lead STA signoff for blocks and full-chip.

The role requires close collaboration with RTL, PD and DFT teams, hands-on experience with PrimeTime/Tempus, Formality/Conformal and at least two tape-outs, delivering predictable timing closure.

Qualifications

• Bachelor’s or Master’s in Electrical Engineering.
• Hands-on experience with synthesis and STA tools.
• Deep understanding of timing concepts: clocks, exceptions, CDC, derates and variation.
• Experience writing and debugging SDC constraints for complex SoCs.
• Experience with at least two tape-outs.

Responsibilities

• Develop and validate SDC constraints for functional and test modes.
• Run RTL-to-gate synthesis with Design Compiler/Genus and optimise PPA.
• Perform multi-corner, multi-mode STA using PrimeTime or Tempus.
• Analyse and fix timing violations; drive timing ECOs with PD.
• Run formal equivalence (Conformal/Formality) and constraint checks.
• Perform signoff timing including SI, OCV/AOCV/POCV and IR-aware analysis.

Skills

Synthesis

STA

Timing constraints

Signoff

PPA optimization

Scripting

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

Design Compiler

Genus

PrimeTime

Tempus

Conformal/Formality

Job description

Own synthesis, constraints and static timing signoff from RTL through post-route across all corners and modes.

Physical Design San Jose, CA / Austin, TX (USA)

You will develop timing constraints, run logic synthesis with PPA optimisation, and lead static timing analysis and signoff for blocks and full-chip. The role is central to predictable timing closure and requires close coordination with RTL, PD and DFT teams.

What you'll do

• Develop and validate SDC constraints for functional and test modes.
• Run RTL-to-gate synthesis with Design Compiler/Genus and optimise PPA.
• Perform multi-corner, multi-mode STA using PrimeTime or Tempus.
• Analyse and fix timing violations; drive timing ECOs with PD.
• Run formal equivalence (Conformal/Formality) and constraint checks.
• Perform signoff timing including SI, OCV/AOCV/POCV and IR-aware analysis.

What you bring

• Bachelor's or Master's in Electrical Engineering.
• Strong hands-on experience with synthesis and STA tools.
• Deep understanding of timing concepts: clocks, exceptions, CDC, derates and variation.
• Experience writing and debugging SDC constraints for complex SoCs.
• Experience with at least two tape-outs.

Nice to have

• Experience with hierarchical timing (ETM/ILM) methodologies.
• Low-power synthesis with UPF.
• Physical-aware synthesis and DFT-aware synthesis.

Why I2Intech

You'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.

Apply

Apply for Synthesis & STA Engineer

Tell us a little about yourself and attach your resume. Our hiring team reviews every application and typically responds within five business days.

1. Application review We match your experience to the role and the partner program. 2. Technical interview A focused conversation with a senior engineer in your discipline. 3. Offer & onboarding Structured onboarding gets you productive on the program fast.

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Cover note

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