Staff Verification Engineer: Automotive Mixed-Signal PMICs

Renesas Electronics Corp.; Arizona; On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Competitive benefits package

Job summary

Renesas Electronics Corp. seeks an experienced Staff Verification Engineer focusing on mixed-signal verification for automotive PMIC devices.

You will model and verify PMICs, switching regulators, and related analog IP, collaborating across Design, Systems, Validation, and CAD teams to ensure successful development, integration, and sign-off of complex power chips. You will design verification environments, implement comprehensive verification plans, and lead debugging of analog blocks while

Responsibilities

• Design and architect mixed-signal verification environments, including RNM and AMS model integration for PMIC designs
• Develop and implement verification plans and strategies for automotive PMIC products per ISO 26262 and AEC-Q200
• Lead debugging for analog blocks such as switched-mode regulators and LDOs
• Set up and optimize Gate-Level Simulation (GLS) flows and correlate with RTL results
• Conduct RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across PVT corners
• Collaborate with Design, Application Engineering, ATE, and Silicon Validation for seamless handoffs
• Troubleshoot complex analog/digital interactions using simulation and measurement techniques
• Drive improvements in verification tools, methodologies, and AI-based solutions
• Create and maintain verification documentation, test plans, and coverage metrics

Job description

Renesas Electronics Corp. seeks an experienced Staff Verification Engineer focusing on mixed-signal verification for automotive PMIC devices.

You will model and verify PMICs, switching regulators, and related analog IP, collaborating across Design, Systems, Validation, and CAD teams to ensure successful development, integration, and sign-off of complex power chips. You will design verification environments, implement comprehensive verification plans, and lead debugging of analog blocks while