Senior Principal Automotive PMIC Verification Lead

Renesas; Plano (TX); On-site; USD 170,000 - 210,000; Full time

Job summary

Renesas is seeking an experienced Senior Principal Design Verification Engineer to lead verification for automotive PMIC products. You will meld analog, digital, and mixed-signal verification while mentoring engineers and shaping verification strategy across platforms.

You will architect mixed-signal verification environments, implement comprehensive plans, and optimize GLS flows, collaborating with Design, ATE, and Silicon Validation to ensure robust verification and timely delivery.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in mixed-signal or analog circuit verification.
• Hands-on with RNM and AMS model integration.
• Proficiency in RTL and behavioral simulation tools like Spectre, Xcelium.

Responsibilities

• Design and architect mixed-signal verification environments, including RNM and AMS integration for PMIC designs.
• Develop and implement verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200).
• Set up and optimize Gate-Level Simulation (GLS) flows, correlating RTL results to identify discrepancies.
• Lead debugging activities for analog blocks such as switched‑mode regulators and LDOs, and mixed-signal interfaces.
• Conduct RTL and Gate-Level simulations across PVT corners, coordinating with cross-functional teams to ensure seamless verification handoffs.
• Mentor junior verification engineers and establish best practices in verification methodologies.

Skills

Mixed-signal verification

RTL/behavioral simulation

Verilog SystemVerilog

UVM

Leadership

Education

MS/PhD in Electrical/Computer Engineering

Tools

Spectre

Xcelium

Job description

Renesas is seeking an experienced Senior Principal Design Verification Engineer to lead verification for automotive PMIC products. You will meld analog, digital, and mixed-signal verification while mentoring engineers and shaping verification strategy across platforms.

You will architect mixed-signal verification environments, implement comprehensive plans, and optimize GLS flows, collaborating with Design, ATE, and Silicon Validation to ensure robust verification and timely delivery.