Staff Mixed-Signal Verification Engineer: Power ICs

Renesas; Chandler (AZ); On-site; USD 140,000 - 190,000; Full time

Job summary

Renesas is seeking a Staff Mixed Signal Verification Engineer to advance verification of PMICs and power-management IP in Chandler, AZ. You will collaborate with design, systems, CAD, and customer teams to drive successful development and sign-off of complex mixed-signal devices.

You will lead analog/mixed-signal verification using AMS and DMS methods, develop SystemVerilog RNM and Verilog-AMS models, and drive verification plans toward tapeout sign-off while mentoring others on complex silicon

Qualifications

• 8–12+ years of experience in mixed-signal verification, AMS/DMS simulation, behavioral modeling or related semiconductor design activities.
• Strong experience with switching regulators, battery chargers, PMICs and mixed-signal verification sign-off methodologies.
• Proficiency with SystemVerilog, Verilog-AMS, UVM, Cadence Xcelium and simulation-driven debug.

Responsibilities

• Lead chip-level verification of analog and mixed-signal circuits using AMS and DMS methodologies.
• Develop verification strategies, drive coverage closure, and support tapeout milestones.
• Create, maintain, and validate behavioral models using SystemVerilog RNM and Verilog-AMS.
• Develop and execute verification plans with full traceability from design requirements through tapeout sign-off.
• Own debugging and root-cause analysis of mixed-signal verification issues across teams.

Skills

Communication

Teamwork

Customer-facing

Education

B.S./M.S. in Electrical/Computer Engineering

Tools

Cadence Xcelium

Spectre

SystemVerilog

Verilog-AMS

UVM

Job description

Renesas is seeking a Staff Mixed Signal Verification Engineer to advance verification of PMICs and power-management IP in Chandler, AZ. You will collaborate with design, systems, CAD, and customer teams to drive successful development and sign-off of complex mixed-signal devices.

You will lead analog/mixed-signal verification using AMS and DMS methods, develop SystemVerilog RNM and Verilog-AMS models, and drive verification plans toward tapeout sign-off while mentoring others on complex silicon