Senior Mixed-Signal Verification Engineer

Renesas Electronics; Chandler (AZ); On-site; USD 140,000 - 170,000; Full time

Benefits offered by this job

Competitive benefits

Job summary

Renesas Electronics seeks an experienced Mixed-Signal Verification Engineer to verify and model PMICs, battery chargers, and related analog IP. You will lead chip-level verification using AMS/DMS methods, integrating analog models with digital RTL/UVM environments.

You will develop verification plans, drive coverage, and own debugging across design, modeling, and verification teams, while collaborating with CAD and system architects to improve verification quality.

Qualifications

• 8-12+ years of experience in mixed-signal verification, AMS/DMS simulation, or related semiconductor design activities.
• Experience with PMICs, battery chargers, switching regulators, or power-management IP is highly desirable.

Responsibilities

• Verify and model mixed-signal power management devices including PMICs, battery chargers, and related analog IP.
• Lead chip-level verification using AMS/DMS methodologies and integrate analog behavioral models with digital RTL/UVM environments.
• Develop verification plans with traceability from requirements through coverage closure and tapeout sign-off.
• Own debugging and root-cause analysis of mixed-signal verification issues across teams.
• Collaborate with analog/digital designers, system architects, and CAD teams to improve modeling accuracy and verification quality.
• Participate in design reviews and optimize topology from a verification perspective.

Skills

Mixed-signal verification

AMS/DMS verification

Communication and collaboration

Education

B.S./M.S. Electrical Engineering

Tools

Cadence Xcelium

Spectre

SystemVerilog

Verilog-AMS

UVM

Job description

Renesas Electronics seeks an experienced Mixed-Signal Verification Engineer to verify and model PMICs, battery chargers, and related analog IP. You will lead chip-level verification using AMS/DMS methods, integrating analog models with digital RTL/UVM environments.

You will develop verification plans, drive coverage, and own debugging across design, modeling, and verification teams, while collaborating with CAD and system architects to improve verification quality.