Lead Mixed-Signal Verification for Automotive PMIC

Renesas Electronics Corp.; Plano (TX); On-site; USD 160,000 - 230,000; Full time

Job summary

Renesas Electronics Corp. in Plano, TX seeks a Principal Verification Engineer to lead verification for the Automotive PMIC product line, combining mixed-signal expertise with leadership to mentor engineers and define strategy.

The role requires deep analog, digital, and mixed-signal verification know-how, RNM/AMS integration, GLS, UVM, and strong debugging across PVT corners; you will collaborate with Design, ATE, and Silicon Validation.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years in mixed-signal or analog circuit verification.
• Proficiency with RNM and AMS model integration.
• RTL and behavioral simulation tools such as Spectre and Xcelium.
• Strong GLS flows: setup, debug, and validation.
• Verilog/SystemVerilog and SPICE-based languages.
• UVM, assertions, and coverage-driven verification.
• Experience with automotive PMIC design/verification.
• Leadership and mentoring experience.

Responsibilities

• Design and architect mixed-signal verification environments.
• Develop verification plans for automotive PMIC products.
• Set up Gate-Level Simulation flows aligned with RTL results.
• Lead debugging of analog blocks like LDOs and switched-mode regulators.
• Run RTL and Gate-Level simulations across PVT corners.
• Mentor junior verification engineers and establish best practices.
• Collaborate with Design, ATE, and Silicon Validation teams.
• Drive verification toolchains, methodologies, and AI-based ideas.
• Create verification documentation and coverage reports.

Skills

RNM/AMS integration

RTL/behavioral sim

GLS flows

Verilog/SystemVerilog

UVM/ Assertions/ Coverage

Leadership/Mentoring

Education

MS/PhD in EE or CE

Tools

Spectre

Xcelium

SPICE

Job description

Renesas Electronics Corp. in Plano, TX seeks a Principal Verification Engineer to lead verification for the Automotive PMIC product line, combining mixed-signal expertise with leadership to mentor engineers and define strategy.

The role requires deep analog, digital, and mixed-signal verification know-how, RNM/AMS integration, GLS, UVM, and strong debugging across PVT corners; you will collaborate with Design, ATE, and Silicon Validation.