Staff Mixed-Signal Verification Lead (Automotive PMICs)

Renesas Electronics Corp.; Chandler (AR); On-site; USD 110,000 - 160,000; Full time

Job summary

Renesas Electronics Corp. is seeking an experienced Staff Verification Engineer to verify and model mixed-signal automotive PMICs, switching regulators, and related analog IP.

You will work with design, systems, validation, and CAD teams to ensure successful development and sign-off of complex mixed-signal power chips. The role requires leading debugging of analog blocks, setting up GLS flows, and conducting RTL and Gate-Level simulations across PVT corners, while driving verification tool

Qualifications

• Expertise in mixed-signal verification for automotive PMICs and associated IP.
• Familiarity with real-number models (RNM) and analog mixed-signal (AMS) integration.
• Experience with RTL and GS timing, power, and functional correctness across PVT corners.

Responsibilities

• Design and architect mixed-signal verification environments (RNM/AMS).
• Develop verification plans for automotive PMIC products including ISO 26262/AEC-Q200 compliance.
• Lead debugging for analog blocks like switched-mode regulators and LDOs; optimize GLS flows.
• Correlate GLS with RTL simulations to resolve discrepancies; analyze timing/power.
• Collaborate with Design, ATE, Silicon Validation for verification handoffs.
• Troubleshoot analog-digital interaction using simulations and measurements.
• Pursue ongoing verification tool improvements and AI-based solutions.
• Create verification documentation, plans, and coverage metrics.

Skills

Mixed-signal verification

PMIC understanding

RTL simulation

GLS flows

PVT analysis

Analog-digital debug

AI-based verification

Tools

RNM

AMS model

Gate-Level Simulation

Job description

Renesas Electronics Corp. is seeking an experienced Staff Verification Engineer to verify and model mixed-signal automotive PMICs, switching regulators, and related analog IP.

You will work with design, systems, validation, and CAD teams to ensure successful development and sign-off of complex mixed-signal power chips. The role requires leading debugging of analog blocks, setting up GLS flows, and conducting RTL and Gate-Level simulations across PVT corners, while driving verification tool