Senior ASIC/SoC Physical Design Engineer - PPA Optimizer

Global IT Con. LLC; Sunnyvale (CA); On-site; USD 170,000 - 230,000; Full time

Job summary

Prodapt, a global AI-first technology partner, is seeking a Senior Physical Design Engineer in Sunnyvale, CA. You will lead RTL synthesis, timing optimization, and floor planning for advanced ASIC/SoC designs, collaborating with RTL, architecture, verification, and PD teams to ensure successful convergence.

This onsite Full-time role offers challenging design responsibilities, close interaction with a world-class silicon team, and competitive compensation with benefits.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of hands-on ASIC/SoC physical design experience.
• Expertise in RTL synthesis and timing optimization.
• Solid experience with floor planning for advanced technology nodes.

Responsibilities

• Drive RTL synthesis and optimization to achieve performance, power, and area goals.
• Perform floor planning for complex ASIC/SoC designs ensuring timing, congestion, and power delivery.
• Collaborate with RTL design engineers to provide feedback improving RTL quality and implementation.
• Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency.
• Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure design convergence.
• Support timing closure by identifying bottlenecks and recommending design improvements.
• Participate in design reviews and contribute to process and methodology improvements.

Skills

ASIC/SoC physical design

RTL synthesis

Floor planning

Timing optimization

Education

Bachelor's or Master's in EE / CE

Tools

EDA tools (Synthesis/PD)

Job description

Prodapt, a global AI-first technology partner, is seeking a Senior Physical Design Engineer in Sunnyvale, CA. You will lead RTL synthesis, timing optimization, and floor planning for advanced ASIC/SoC designs, collaborating with RTL, architecture, verification, and PD teams to ensure successful convergence.

This onsite Full-time role offers challenging design responsibilities, close interaction with a world-class silicon team, and competitive compensation with benefits.