Staff Physical Design Engineer: AI-Driven Tapeout Expert

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Health benefits

Wellness program

Financial benefits

Job summary

Synopsys, Inc. in Sunnyvale seeks a Senior RTL-to-GDS Engineer to drive physical design from RTL through tapeout using Fusion Compiler and related tools. You will work with senior engineers to resolve complex P&R and timing challenges for advanced nodes, ensuring first-pass silicon success.

You will script in TCL/Python to automate workflows, apply AI-assisted methods, and collaborate with customers to meet aggressive tapeout timelines while optimizing power, performance, and area.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 5+ years hands-on ASIC/physical design or CAD engineering experience.
• Experience with RTL-to-GDS implementations and timing closure.
• Proficiency with TCL and Python scripting for automation.
• Strong English communication and customer-facing skills.

Responsibilities

• Support physical design implementation and design closure using Synopsys tools.
• Debug timing, power, congestion, and routing challenges at advanced nodes (5nm+).
• Guide customers toward implementation closure within tapeout schedules.
• Provide technical guidance on synthesis, P&R, timing closure, and power optimization.
• Develop automation scripts in TCL to streamline workflows.
• Apply AI-powered workflows to accelerate issue resolution and productivity.
• Collaborate with R&D to reproduce issues and feed real-world use cases back to product teams.
• Present solutions to senior engineers and design leads during critical phases.
• Work across RTL-to-GDS flow through signoff and tapeout readiness.

Skills

RTL2GDS flow

Place-and-route

Timing closure

Debugging P&R issues

Fusion Compiler

ICC2

Formality

PrimeTime

TCL scripting

Python scripting

AI-assisted workflows

Customer collaboration

Business English

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

Fusion Compiler

ICC2

Formality

PrimeTime

Job description

Synopsys, Inc. in Sunnyvale seeks a Senior RTL-to-GDS Engineer to drive physical design from RTL through tapeout using Fusion Compiler and related tools. You will work with senior engineers to resolve complex P&R and timing challenges for advanced nodes, ensuring first-pass silicon success.

You will script in TCL/Python to automate workflows, apply AI-assisted methods, and collaborate with customers to meet aggressive tapeout timelines while optimizing power, performance, and area.