Senior Physical Design Applications Engineer

Synopsys Inc; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys Inc. in Sunnyvale, CA seeks a senior ASIC physical design engineer to engage directly with customers, drive advanced node flows, and optimize designs using Fusion Compiler and ICC2.

You will work across the RTL-to-GDS chain, tackle timing, routing, and power challenges, and mentor teams on best practices. Required 7+ years of hands-on ASIC PD experience, deep understanding of 7nm+ nodes, and excellent communication skills to translate complex technical issues into actionable plans for

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent; 7+ years hands-on ASIC physical design experience.
• Deep experience with RTL-to-GDS flows including placement, optimization, clock tree synthesis, and routing.
• Hands-on experience with Synopsys backend tools, especially Fusion Compiler or ICC2, and timing closure, macro placement, and routing at advanced nodes.
• Proficiency with static timing analysis tools, particularly PrimeTime, including setup/hold and noise analysis.
• Solid understanding of 7nm+ node design challenges (FinFETs, multi-patterning, electromigration).
• Experience with logical and physical synthesis flows and AI-driven optimization methodologies.

Responsibilities

• Support customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler to help achieve PPA targets on advanced node designs.
• Debug complex physical design issues across RTL-to-GDS flow including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and below.
• Develop and deliver methodology recommendations tailored to customer design constraints, process technologies, and project schedules.
• Run benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologies.
• Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature requests.
• Present technical content to customer engineering teams and management, translating tool capabilities into business outcomes.
• Travel to customer sites as needed to provide onsite support, training, and design reviews.

Skills

ASIC physical design

RTL-to-GDS flows

Fusion Compiler / ICC2

PrimeTime

Education

Bachelor's degree in Electrical Engineering or equivalent

Master's degree with 5+ years

Tools

Fusion Compiler

ICC2

Design Compiler

PrimeTime

Job description

Synopsys Inc. in Sunnyvale, CA seeks a senior ASIC physical design engineer to engage directly with customers, drive advanced node flows, and optimize designs using Fusion Compiler and ICC2.

You will work across the RTL-to-GDS chain, tackle timing, routing, and power challenges, and mentor teams on best practices. Required 7+ years of hands-on ASIC PD experience, deep understanding of 7nm+ nodes, and excellent communication skills to translate complex technical issues into actionable plans for