Senior Applications Engineer - Pre-Sales, Physical Design

Synopsys Inc; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys Inc. in Sunnyvale, CA seeks a senior ASIC physical design engineer with 9+ years of hands-on experience in RTL-to-GDSII flows, clock tree synthesis, placement, and routing.

You will work directly with design teams using Fusion Compiler, ICC2, Design Compiler, and PrimeTime to drive timing closure and PPA improvements. You will travel up to 30% to customer sites, translate customer pain points into feature requests, and mentor junior engineers as part of the Customer Success Group.

Qualifications

• Experience with RTL-to-GDSII flows and standard physical design toolchains.
• Proven ability to close timing on advanced nodes (7nm and below).
• Strong debugging skills for placement, routing, and congestion issues.

Responsibilities

• Support RTL-to-GDSII flow issues across the design teams to meet timing and PPA targets.
• Develop and deliver clock tree synthesis methodologies and timing closure strategies.
• Collaborate with product engineers to translate customer pain points into tool enhancements.
• Build proof-of-concept designs and benchmarks showing PPA improvements.
• Teach customers and internal teams advanced tool capabilities including multi-scenario optimization.
• Travel to customer sites up to 30% for on-site support during critical phases.

Skills

RTL-to-GDSII flows

Clock tree synthesis

Routing

Placement

Timing closure

Multi-node 7nm+

Debugging tape-outs

Travel readiness

Education

Bachelor's degree in Electrical Engineering or equivalent

Master's degree (preferred)

Tools

Fusion Compiler

ICC2

Design Compiler

PrimeTime

Job description

Synopsys Inc. in Sunnyvale, CA seeks a senior ASIC physical design engineer with 9+ years of hands-on experience in RTL-to-GDSII flows, clock tree synthesis, placement, and routing.

You will work directly with design teams using Fusion Compiler, ICC2, Design Compiler, and PrimeTime to drive timing closure and PPA improvements. You will travel up to 30% to customer sites, translate customer pain points into feature requests, and mentor junior engineers as part of the Customer Success Group.