Staff Package Design Engineer: SoC & SiP Innovation

Qualcomm; Santa Clara (CA); On-site; USD 154,000 - 252,800; Full time

Job summary

Qualcomm is seeking a Staff Package Design Engineer in Santa Clara to own advanced package selection and SIP/SoC packaging. You will drive physical design, layout, DV, and tape-out, collaborating with multi-functional teams to optimize mechanical, electrical, and thermal performance for various chip types.

The role requires expertise in Cadence APD/SiP, Xpedition, and Calibre, with a strong background in high-speed interfaces (DDR, PCIe).

Qualifications

• Master's degree in electrical engineering, mechanical engineering, material science, or related fields with 5+ years of experience.
• Fundamentals in electrical, material, thermal, or mechanical engineering fields.
• Familiarity with various sophisticated package configurations and assembly/substrate technology (Flip chip BGA, 2.5D/3D Interposer).
• Experience in package design and proficiency in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP).
• Basic understanding of SI/PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.), package model extraction, S-parameters, and RLGC model.
• Knowledge of substrate manufacturing process, structure, design rules, and material properties.
• Proven understanding of high-speed interfaces (DDR, PCIe, UCIE).
• Experience with Calibre tool and package design reviews.

Responsibilities

• Own and drive advanced package selection, new generation product package structure, and configuration optimization.
• Responsible for Package/SIP physical design and layout, optimization, DV, and tape out.
• Work with multi-functional teams to achieve optimized mechanical, electrical, and thermal performance for various types of chips.
• Implement the physical design of packages and modules for SoC.
• Interface and coordinate with multi-functional groups on feasibility analysis, design, and selection.
• Define and develop design verification and automation strategy to strengthen and streamline release flows.
• Work with teams to optimize package pin out and interface requirements.
• Drive improvements in package design with vendors and developers on feature development and bug resolution.

Skills

Cadence APD/SiP

Constraint Manager

Inline DRC/DFM

High-speed signal integrity

DDR/PCIe interfaces

SiP/Package design

Calibre

Xpedition (Siemens)

Education

Master's degree in Electrical Engineering / Mechanical Engineering / Materials Science

Tools

Cadence Allegro

XtractIM

HFSS

Q3D

Calibre

Job description

Qualcomm is seeking a Staff Package Design Engineer in Santa Clara to own advanced package selection and SIP/SoC packaging. You will drive physical design, layout, DV, and tape-out, collaborating with multi-functional teams to optimize mechanical, electrical, and thermal performance for various chip types.

The role requires expertise in Cadence APD/SiP, Xpedition, and Calibre, with a strong background in high-speed interfaces (DDR, PCIe).