Staff Engineer - Microarchitectural Validation & DV Strategy

Kindredventures; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Competitive salary

Meaningful equity stake

Autonomy and visible impact

Job summary

Architect Labs seeks a Technical Staff member to own the verification strategy for AI-generated designs tape-out on leading foundries. You will work at the intersection of hardware verification and AI-driven design automation, defining DV flows and reusable collateral across IPs.

You will collaborate with architecture, design, and AI/ML leads to ensure simulation- and emulation-ready collateral scales across projects, while staying ahead of industry trends in pre-/post-silicon verification.

Qualifications

• Degree in Electrical/Computer Engineering or closely related field.
• 5+ years of tapeout experience on advanced-node SoCs; 10+ preferred.
• Deep expertise in verification/validation, emulation, and IP/SoC validation platforms.
• Strong coding skills in SystemVerilog, UVM, C/C++, and Python.
• Hands-on verification experience across CPUs, memory controllers, and interconnects.
• Ability to map IP/SoC designs to FPGA prototypes for fast validation.

Responsibilities

• Define and drive DV/verification strategy for AI-generated designs tape-out.
• Coordinate validation flows across multiple IPs and projects.
• Develop modular, reusable validation collateral and checkers.
• Collaborate with architecture, design, and AI/ML leads for collaterals.
• Track trends in semiconductor verification to keep methods cutting-edge.

Skills

SystemVerilog

UVM

C/C++

Python

DV strategy

Verification leadership

Education

Bachelor's or higher in Electrical/Computer Engineering

Tools

Xilinx Vivado

Emulation tools

FPGA prototyping

Job description

Architect Labs seeks a Technical Staff member to own the verification strategy for AI-generated designs tape-out on leading foundries. You will work at the intersection of hardware verification and AI-driven design automation, defining DV flows and reusable collateral across IPs.

You will collaborate with architecture, design, and AI/ML leads to ensure simulation- and emulation-ready collateral scales across projects, while staying ahead of industry trends in pre-/post-silicon verification.