Design Verification Engineer - AI Accelerator ASIC/SoC

Acceler8 Talent; San Francisco (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Competitive equity package

Medical, dental, vision coverage

401(k) plan

Generous paid time off

Job summary

Acceler8 Talent is partnering with a well-funded, early-stage AI hardware startup to hire a Design Verification Engineer. You’ll own verification for major functional areas, collaborating with architecture, RTL, and software to ensure first-pass silicon success and scalable verification practices.

You’ll define verification strategies across IP, subsystems, and full-chip, build reusable UVM environments, and drive functional closure.

Qualifications

• 5+ years of hands-on pre-silicon verification on complex ASIC/SoC programs.
• Strong knowledge of IP, subsystem, and full-chip verification.
• Experience with hardware emulation and NoC/Die-to-Die verification is a plus.

Responsibilities

• Own verification for a major functional area with depth in architecture-driven tests.
• Define and execute verification strategies across IP, subsystem, SoC, and emulation.
• Build AI-assisted verification workflows to boost productivity and reduce cycle times.
• Develop reusable UVM-based environments, test plans, stimuli, and coverage models.
• Drive functional closure by debugging design issues with design and architecture teams.
• Contribute to scalable verification methodologies for future silicon programs.

Skills

UVM

Constrained-random verification

Testbench architecture

AI-assisted verification

Tools

Cadence Palladium

Siemens Veloce

Job description

Acceler8 Talent is partnering with a well-funded, early-stage AI hardware startup to hire a Design Verification Engineer. You’ll own verification for major functional areas, collaborating with architecture, RTL, and software to ensure first-pass silicon success and scalable verification practices.

You’ll define verification strategies across IP, subsystems, and full-chip, build reusable UVM environments, and drive functional closure.