Chip Design and Verification Methodology Engineer

TenX Semi; San Francisco (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

TenX Semi is seeking a Chip Design and Verification Methodology Engineer in the San Francisco Bay Area. You will develop innovative methodologies to design and verify chip designs, focusing on AI-generated RTL verification and maximal automation.

You will architect verification loops, establish reusable test environments, and build convergence monitoring, deep-dive debugging tools, and formal proof generation to ensure robust, trustworthy chip designs.

Qualifications

• Fluency in Verilog and SystemVerilog for design and verification TBs.
• Strong experience with SystemVerilog Assertions for complex protocols.
• Deep experience with UVM including constrained-random verification and coverage.
• Solid understanding of pipelines, FSMs, clock domain crossing, and memory hierarchy.
• Ability to read and analyze waveforms to root cause issues and feed AI models.

Responsibilities

• Drive Verification Methodology and Environment for AI-generated RTL with high automation.
• Architect test environments that scale across customer designs and integrate simulation, formal, and emulation.
• Build convergence monitoring to measure coverage and define when AI-generated designs are complete.
• Develop tools to parse and analyze waveforms and trace signal dependencies for root causes.
• Collaborate with AI engineers to ensure verification feedback improves model accuracy.
• Produce formal proofs for critical paths ensuring safety-critical properties hold.

Skills

Verilog/SystemVerilog

SystemVerilog Assertions

UVM

Computer Architecture

Waveform Analysis

Automation / Python

Education

MS/PhD in Electrical Engineering or Computer Science

Tools

Verdi/SIMVision/DVE

JasperGold or VC Formal

Job description

Chip Design and Verification Methodology Engineer

San Francisco Bay Area, CA · Hybrid · Full-time

We are looking for a Chip Design and Verification Methodology Engineer who develops innovative methodologies to design and verify chip designs with a massive boost in productivity and quality. We treat verification as a design discipline in a holistic manner—not just a testing phase.

In this role, you will ensure the functional correctness of AI-generated RTL while fundamentally changing the way we design and verify chips. You will architect the verification loop that performs maximal automation, finds the "impossible" bugs, proves correctness, and lays the foundation for improving power-performance-area (PPA) rapidly. Your work is the foundation that makes AI-generated chip design usable and trustworthy.

What You Will Do

• Drive Verification Methodology and Environment: Take responsibility for the full verification lifecycle of AI-generated RTL with maximal automation. You will build the verification loop that catches bugs, generates actionable feedback, and enables AI models to improve.
• Architect Test Environments: Write clean, modular, and reusable verification environments/harnesses that can scale across customer designs. Your environments will integrate simulation, formal verification, and emulation into a unified flow.
• Build Convergence Monitoring: Develop systems that track verification progress, measure coverage, and provide guarantees about design correctness. You will define what "done" means for AI-generated designs.
• Deep-Dive Debugging: Go beyond pass/fail logs. You will build advanced tools to read, parse, and analyze waveforms, tracing signal dependencies to pinpoint the root cause of logic failures and feed actionable information back to AI models.
• Collaborate on AI Integration: Work closely with AI engineers to ensure verification feedback improves model accuracy. Your understanding of what makes RTL correct will shape how our AI learns.
• Formal Proof Generation: Develop formal proofs for critical design paths, ensuring that safety‑critical properties hold under all conditions.

What You Bring (Required)

• Verilog and SystemVerilog Fluency: You have expert-level proficiency in writing Verilog and SystemVerilog. You understand the nuances of the language for both design (RTL) and verification (TB).
• SystemVerilog Assertions: You have strong experience writing SystemVerilog Assertions. You know how to write concurrent assertions to validate complex temporal protocols.
• UVM Expertise: You have deep experience with UVM methodology, including constrained‑random verification, functional coverage, and scoreboards.
• Computer Architecture Fundamentals: You possess a solid understanding of Computer Architecture and Digital Design fundamentals (e.g., pipelines, FSMs, clock domain crossing, memory hierarchy, and coherence protocols).
• Waveform Analysis: You have proven ability to read and analyze simulation waveforms (using tools like Verdi, SimVision, or DVE) to resolve complex logic issues.
• Automation Mindset: You have strong Python/scripting skills and a passion for automating everything that can be automated.

Bonus Points (Preferred)

• Hands‑on experience with commercial formal tools such as JasperGold or VC Formal. Experience with formal apps (Connectivity, CDC, RDC, CSR) is highly desirable.
• Deep knowledge of standard on‑chip interface protocols like AXI, AHB, APB, CHI, PCIe, or CXL.
• Experience at EDA vendors (Synopsys, Cadence, Siemens) or leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm).
• Background in emulation platforms (Palladium, Veloce, ZeBu).
• Familiarity with AI/ML concepts and interest in how AI can transform chip design.
• MS or PhD in Electrical Engineering or Computer Science.

Why Join Us

You will be building the foundation of a new way to design chips. Verification is what makes AI-generated RTL trustworthy—your work enables everything else. You'll work at the intersection of traditional chip verification and cutting‑edge AI, solving problems no one has solved before.