Staff Engineer, Microarchitectural Validation & DV Strategy

Architect Labs; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Equity stake

Competitive salary

Autonomy in startup

Job summary

Architect seeks a Technical Staff member to own verification strategy for AI-generated designs taping out on leading foundries. You will work at the intersection of hardware verification and AI-driven design automation, contributing to end-to-end DV across multiple IPs.

Ideal candidates have 5+ years tapeout experience and strong SystemVerilog/UVM/C/C++ skills, with Python preferred, and a track record in pre/post-silicon verification and collaboration with AI teams.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering or Computer Engineering.
• Tapeout experience: 5+ years (10+ preferred) working on advanced-node tapeouts at top chip companies or fast-moving silicon startups.
• End-to-end silicon delivery is a strong plus.
• Verification expertise: Deep expertise in verification/validation, emulation, and architectural and system-level verification of industry-standard IPs.
• Proven track record defining microarchitectural checkers and monitors, modeling IP and SoC validation platforms, and developing modular, reusable validation collateral.
• Coding: Strong skills in SystemVerilog, UVM, and C/C++ for test environments. Python strongly preferred.
• Subsystem Depth: Hands-on verification experience in at least one of the following areas: ARM/AMBA protocols, CPU subsystems, Memory controllers and PHY, On-chip interconnect / NoC, NPU / ML accelerator cores, Security IPs.
• Methodology: Hands-on experience with simulation and emulation flows and methodologies. Experience mapping IP and SoC designs to FPGA prototypes for fast functional verification.
• Execution: Excellent problem-solving, collaboration, and communication skills with strong attention to detail. Ability to work independently and drive cross-functional alignment.
• Leadership: Ability and desire to lead the DV function over time as the team scales.

Responsibilities

• Review AI-driven test plan and validation strategy for internal and external SoC projects.
• Provide domain-specific expertise to our AI/ML teams, including architectural and microarchitectural checks, validation modularity, checkers, coverage models, and interface protocols — helping encode DV best practices into our AI-driven flows.
• Independently define, drive, and coordinate validation, verification, and integration flows across multiple IPs, including checkpoints and collateral handoffs.
• Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral that scales across projects.
• Track emerging trends in semiconductor verification and AI-driven design automation to keep our methodology cutting-edge in quality, scalability, and throughput.

Skills

Tapeout experience

Verification expertise

SystemVerilog/UVM/C/C++

Python

ARM/AMBA protocols

CPU subsystems

Memory controllers/NoC

NPU/ML accelerator cores

Security IPs

Leadership

Education

Bachelor's/Master's/PhD in Electrical or Computer Engineering

Tools

FPGA prototyping (Xilinx Vivado/Vitis)

Job description

Architect seeks a Technical Staff member to own verification strategy for AI-generated designs taping out on leading foundries. You will work at the intersection of hardware verification and AI-driven design automation, contributing to end-to-end DV across multiple IPs.

Ideal candidates have 5+ years tapeout experience and strong SystemVerilog/UVM/C/C++ skills, with Python preferred, and a track record in pre/post-silicon verification and collaboration with AI teams.