Staff DV Engineer: High-Perf CPU Core with RVV

SiFive, Inc.; Austin (TX); On-site; USD 150,000 - 190,000; Full time

Job summary

SiFive is seeking a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality with a focus on RVV and vector microarchitecture. This individual-contributor role collaborates with architecture, RTL, performance, and verification teams to ensure design intent is captured and corner cases are thoroughly verified, while maintaining scalable verification methodologies.

The role spans Frontend, Midcore, Load-Store Unit, and Vector Unit interactions, requiring

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification for Staff role.
• Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.
• Direct experience with CPU/core verification and understanding of computer architecture.
• Experience in Frontend, Midcore, Load-Store Unit, memory ordering or Vector Unit verification.
• Proficiency in verification flow: test planning, stimulus generation, failure analysis, coverage.
• Familiarity with Python, C/C++, or similar scripting languages used for DV infrastructure.

Responsibilities

• Own verification planning and execution for high-performance out-of-order CPU core areas from block-level to core-level signoff.
• Drive verification strategy, test planning, debugging, coverage analysis, and closure for complex CPU features.
• Verify RVV and vector-unit functionality including vector arithmetic, memory ops, masking, and configuration-dependent execution.
• Develop robust verification environments, checkers, scoreboards, and coverage models.
• Collaborate with architecture and design teams to review specs and improve verification completeness.
• Mentor engineers through reviews, debugging guidance, and verification practices.

Skills

SystemVerilog DV

CPU core verification

Vector unit verification

Debugging skills

Mentoring

Python

C/C++ scripting

Education

BS/MS in EE/CE/CS

Tools

Python

C/C++

Verilog

Job description

SiFive is seeking a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality with a focus on RVV and vector microarchitecture. This individual-contributor role collaborates with architecture, RTL, performance, and verification teams to ensure design intent is captured and corner cases are thoroughly verified, while maintaining scalable verification methodologies.

The role spans Frontend, Midcore, Load-Store Unit, and Vector Unit interactions, requiring