Senior CPU Core DV Engineer - RVV & Vector Verification

SiFive; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Healthcare

401(k) plan

Paid time off

Job summary

SiFive is seeking a Senior Design Verification Engineer to drive verification of high‑performance CPU core functionality, with meaningful scope in RVV and vector microarchitecture verification.

This role is within the CPU Design Verification organization and focuses on high‑performance out‑of‑order CPU core development, including Frontend, Midcore, Load‑Store Unit, Hardware Prefetch, and Vector Unit interactions.

Qualifications

• Proficiency in SystemVerilog-based verification and modern verification methodologies.
• Ability to plan verification strategies and develop test content.
• Strong debugging and scripting fundamentals for scalable verification solutions.

Responsibilities

• Own verification planning and execution for high‑performance CPU core areas from block- to core-level integration.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Define and execute directed and constrained‑random tests to expose corner cases in branch prediction, fetch, pipeline, memory ordering, and vector execution.
• Drive verification of RVV and vector-unit functionality including SEW, LMUL, VL, VSTART, masking, and scalar‑vector interactions.
• Collaborate with architecture and RTL teams to review specifications and ensure signoff quality.

Skills

SystemVerilog

DV planning

Debugging

RVV verification

CPU architecture

Scripting

Education

Bachelor's or Master’s in EE/CE/CS

Job description

SiFive is seeking a Senior Design Verification Engineer to drive verification of high‑performance CPU core functionality, with meaningful scope in RVV and vector microarchitecture verification.

This role is within the CPU Design Verification organization and focuses on high‑performance out‑of‑order CPU core development, including Frontend, Midcore, Load‑Store Unit, Hardware Prefetch, and Vector Unit interactions.