Staff CPU Core DV Engineer: RVV Vector & OoO

Sifive; Austin (TX); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Health insurance

401(k) plan

Equity compensation

Job summary

SiFive, the pioneer of RISC-V, seeks a Staff Design Verification Engineer to drive verification of high-performance CPU cores, focusing on RVV and vector microarchitecture.

In this staff role, you will own verification across frontend, midcore, load-store, and vector unit interactions, collaborating with architecture, RTL, and performance teams to ensure robust verification and sign-off.

Qualifications

• Bachelor’s or Master’s degree in EE/CE/CS.
• 7+ years of ASIC/CPU/core or SoC design verification experience.
• Strong SystemVerilog-based verification skills and modern DV methodologies.
• Experience with CPU core areas and RVV/vector-unit verification.
• Excellent debugging and test-coverage skills.

Responsibilities

• Own verification planning and test execution for high-performance CPU cores.
• Drive verification strategy, test planning, debug, coverage analysis, and closure.
• Develop robust verification environments, checkers, scoreboards, and assertions.
• Collaborate with architecture, RTL, performance teams to ensure design intent and coverage.
• Mentor engineers and contribute reusable DV infrastructure.

Skills

SystemVerilog

Verification

CPU core

RISC-V RVV

Python

C/C++

Debugging

Education

Bachelor's/Master's in EE/CE/CS

Tools

Python

C/C++

Job description

SiFive, the pioneer of RISC-V, seeks a Staff Design Verification Engineer to drive verification of high-performance CPU cores, focusing on RVV and vector microarchitecture.

In this staff role, you will own verification across frontend, midcore, load-store, and vector unit interactions, collaborating with architecture, RTL, and performance teams to ensure robust verification and sign-off.