Staff CPU Core Verification Engineer — RVV/Vector

SiFive; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

SiFive, a leader in RISC-V technology, seeks a Staff Design Verification Engineer in Santa Clara to drive verification for high‑performance CPU cores and RVV vector extensions. You’ll define verification strategy, build test environments, and collaborate with architecture, RTL, and performance teams to ensure robust sign‑off.

The role emphasizes independent ownership of complex verification problems, scalable DV methodology, and mentoring teammates within a high‑performance CPU DV group.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or Computer Science.
• 7+ years of ASIC/CPU/core or SoC design verification experience.
• Strong hands-on experience with SystemVerilog-based verification and modern methodologies.
• Direct experience with CPU/core verification and understanding of computer architecture.

Responsibilities

• Own verification planning and execution for one or more high-performance CPU core areas.
• Drive verification strategy, test planning, debug, coverage analysis, and closure for complex features.
• Define verification approaches for branch prediction, fetch, issue/dispatch, pipeline interactions, and memory ordering.
• Verify RVV/vector-unit functionality including vector arithmetic, masking, and configuration-dependent execution.
• Develop and maintain verification environments, checkers, scoreboards, and coverage models.
• Collaborate with architecture/design teams to improve verification completeness and debugability.
• Mentor engineers and contribute reusable DV infrastructure.

Skills

SystemVerilog-based verification

CPU/core verification

Verification flow

Python scripting

C/C++ programming

Debugging skills

mentoring

Education

Bachelor's or Master’s in EE/CE/CS

Tools

Python

C/C++

SystemVerilog

Job description

SiFive, a leader in RISC-V technology, seeks a Staff Design Verification Engineer in Santa Clara to drive verification for high‑performance CPU cores and RVV vector extensions. You’ll define verification strategy, build test environments, and collaborate with architecture, RTL, and performance teams to ensure robust sign‑off.

The role emphasizes independent ownership of complex verification problems, scalable DV methodology, and mentoring teammates within a high‑performance CPU DV group.