Senior CPU Core DV Engineer - RVV & Vector Unit

SiFive, Inc.; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Job summary

SiFive is seeking a Senior Design Verification Engineer to drive verification of high‑performance CPU core functionality with emphasis on RVV vector extension and vector microarchitecture verification. You will work with architecture, RTL, performance, and verification teams to verify design intent and achieve signoff quality.

The role requires 5+ years in CPU/core verification, strong SystemVerilog/UVM expertise, and deep knowledge of computer architecture.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of relevant experience in IP, CPU/core, or SoC functional verification.
• Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.
• Solid understanding of computer architecture and CPU microarchitecture fundamentals.
• Experience with test planning, verification environment development, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
• Strong programming and scripting fundamentals for building scalable verification solutions.
• Experience in one or more CPU core areas such as Frontend, Midcore, Load-Store Unit, memory ordering and consistency, Hardware Prefetch, or Vector Unit verification.

Responsibilities

• Own verification planning and execution for assigned high‑performance CPU core areas, from block‑level verification through core‑level integration.
• Create effective verification strategies and test plans based on CPU architecture and microarchitectural behavior.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Define and execute directed and constrained‑random tests that expose corner cases in branch prediction, instruction fetch, pipeline interactions, issue/dispatch behavior, hazard handling, load/store ordering, memory consistency, hardware prefetch behavior, and vector execution correctness.
• Drive verification of RVV and vector‑unit functionality, including vector arithmetic, vector memory operations, masking behavior, configuration‑dependent execution, hazard handling, exception behavior, and scalar‑vector interactions.
• Verify vector microarchitectural behaviors involving SEW, LMUL, VL, VSTART, masking, vector register‑file behavior, vector memory sequencing, and interaction with the scalar pipeline and cache / memory hierarchy.
• Analyze failures, isolate root cause, and drive fixes across RTL, verification infrastructure, assertions, and test content.
• Collaborate closely with architecture and design teams to review specifications, identify ambiguities early, and improve verification quality and debugability.
• Write functional coverage, analyze code and functional coverage, and close coverage gaps to ensure verification completeness and signoff quality.
• Contribute reusable DV methodology, automation, and infrastructure that improve team productivity and verification quality across future CPU core generations.

Skills

SystemVerilog

CPU verification

Debugging

Scripting

Verification planning

Education

Electrical Engineering

Tools

SystemVerilog

UVM

Verilog

Job description

SiFive is seeking a Senior Design Verification Engineer to drive verification of high‑performance CPU core functionality with emphasis on RVV vector extension and vector microarchitecture verification. You will work with architecture, RTL, performance, and verification teams to verify design intent and achieve signoff quality.

The role requires 5+ years in CPU/core verification, strong SystemVerilog/UVM expertise, and deep knowledge of computer architecture.