Senior CPU Core Verification Engineer – RVV & Vector Unit

Sifive; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

SiFive is seeking a Senior Design Verification Engineer to drive verification of high-performance CPU core functionality, with emphasis on RVV and vector microarchitecture. You will own verification across Frontend, Midcore, Load-Store Unit, and Vector Unit interactions, working with architecture, RTL, performance, and verification teams to ensure robust signoff.

The role requires strong SystemVerilog skills, test planning, and the ability to develop reusable DV infrastructure, with a focus on

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of relevant experience in IP, CPU/core, or SoC functional verification.
• Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.

Responsibilities

• Own verification planning and execution for assigned high-performance CPU core areas, from block-level verification through core-level integration.
• Create effective verification strategies and test plans based on CPU architecture and microarchitectural behavior.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Define and execute directed and constrained-random tests that expose corner cases in branch prediction, instruction fetch, pipeline interactions, issue/dispatch behavior, hazard handling, load/store ordering, memory consistency, hardware prefetch behavior, and vector execution correctness.
• Drive verification of RVV and vector-unit functionality, including vector arithmetic, vector memory operations, masking behavior, configuration-dependent execution, hazard handling, exception behavior, and scalar-vector interactions.
• Verify vector microarchitectural behaviors involving SEW, LMUL, VL, VSTART, masking, vector register-file behavior, vector memory sequencing, and interaction with the scalar pipeline and cache / memory hierarchy.

Skills

SystemVerilog

Verification methodologies

CPU architecture

Debugging

Scripting

Education

Bachelor’s or Master’s in Electrical/Computer Engineering or CS

Tools

UVM

RTL Simulation

Job description

SiFive is seeking a Senior Design Verification Engineer to drive verification of high-performance CPU core functionality, with emphasis on RVV and vector microarchitecture. You will own verification across Frontend, Midcore, Load-Store Unit, and Vector Unit interactions, working with architecture, RTL, performance, and verification teams to ensure robust signoff.

The role requires strong SystemVerilog skills, test planning, and the ability to develop reusable DV infrastructure, with a focus on