Staff CPU Core DV Engineer – High-Performance, Equity

SiFive, Inc.; Texas; On-site; USD 140,000 - 210,000; Full time

Job summary

SiFive, Inc. is seeking a Staff Design Verification Engineer to drive verification of high‑performance CPU core units.

This senior individual contributor role spans Frontend, Midcore, Load-Store Unit, and hardware prefetch within the CPU verification team. You will partner with architecture, RTL, performance, and verification teams to capture design intent, identify risks early, and raise verification quality with robust environments, checkers, and coverage models.

Qualifications

• Bachelor’s or Master’s degree in EE, CE, or CS.
• 7+ years of relevant CPU/core verification experience.
• Strong SystemVerilog and UVM experience.
• Deep understanding of computer architecture and CPU microarchitecture.

Responsibilities

• Own verification planning and execution for high-performance CPU core areas.
• Drive block- and core-level verification planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural behavior.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Collaborate with architecture and design teams to review specifications, identify ambiguity, and improve design debugability and verification quality.

Skills

SystemVerilog

UVM

CPU verification

Computer architecture

Debug skills

constrained-random stimulus

Python

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Formal verification

Emulation

Job description

SiFive, Inc. is seeking a Staff Design Verification Engineer to drive verification of high‑performance CPU core units.

This senior individual contributor role spans Frontend, Midcore, Load-Store Unit, and hardware prefetch within the CPU verification team. You will partner with architecture, RTL, performance, and verification teams to capture design intent, identify risks early, and raise verification quality with robust environments, checkers, and coverage models.