Staff Chip-Scale Packaging Engineer (GaN/SiC)

Navitas Semiconductor Usa; Torrance (CA); On-site; USD 135,000 - 165,000; Full time

Job summary

Navitas Semiconductor seeks a Staff Electromechanical Packaging Engineer in Torrance, CA. You will contribute to chip-scale packaging design, HDI substrates, and cross-functional collaboration with layout, ASIC design, and manufacturing teams.

The role requires a BS in mechanical or electrical engineering, 3+ years in microelectronics packaging or PCB design, and familiarity with CAD tools and thermal analysis.

Qualifications

• Minimum BS in Mechanical or Electrical engineering; MS or higher preferred.
• 3+ years' experience with microelectronics packaging and/or PCB design.
• Preferred knowledge of foundry processes and chip-scale assembly processes.

Responsibilities

• Support chip scale packaging design and HDI organic substrate layout for integrated voltage regulator product line.
• Collaborate with substrate layout, ASIC design, and manufacturing engineers.
• Create mechanical drawings for substrate fabrication and packaged part assembly; work with vendors for components, assembly, and test.
• Work with OSAT suppliers in establishing process baseline from prototype to mass production.

Skills

3D CAD

GD&T

Electrical schematics

PCB design familiarity

Thermal analysis (basic)

DFM basics

Substrate layout knowledge

Wafers/substrate familiarity

Education

BS in Mechanical or Electrical Engineering

MS or higher preferred

Tools

Creo

NX

Catia

Altium

Cadence

Mentor

PCB design tools

Job description

Navitas Semiconductor seeks a Staff Electromechanical Packaging Engineer in Torrance, CA. You will contribute to chip-scale packaging design, HDI substrates, and cross-functional collaboration with layout, ASIC design, and manufacturing teams.

The role requires a BS in mechanical or electrical engineering, 3+ years in microelectronics packaging or PCB design, and familiarity with CAD tools and thermal analysis.