Principal DV Lead: Cache-Coherent Interconnect

SiFive; Austin (TX); On-site; USD 231,000 - 283,000; Full time

Job summary

SiFive is seeking a Principal Design Verification Engineer in Austin, TX to lead verification strategy for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms.

This principal tech-lead role spans architecture-aware verification, RTL, formal, performance, and design verification teams to ensure correct data movement, protocol correctness, and robust subsystem integration.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification, with depth appropriate for a Principal / T6 role.
• Strong hands-on experience with SystemVerilog-based verification and reusable verification infrastructure for complex hardware subsystems.
• Strong understanding of cache-coherent systems, on-chip interconnects, CPU memory-subsystem behavior, and verification of ordering, snooping, and flow-control semantics.
• Deep experience creating verification plans, assertions, checkers, scoreboards, coverage models, and debug workflows for complex subsystem-level designs.
• Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
• Strong software, scripting, and automation skills in Python or similar languages for scalable DV infrastructure and workflows.
• Strong technical communication and the ability to work effectively across architecture, RTL, formal, performance, and verification teams.

Responsibilities

• Lead verification planning and execution for a cache-coherent interconnect subsystem from block level through subsystem integration and signoff.
• Define verification strategy, test plans, closure criteria, assertions, checkers, scoreboards, stimulus approaches, and coverage models for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, arbitration, QoS, and error handling.
• Drive verification across interface boundaries, bridges, protocol adaptation layers, and related subsystem data-movement paths.
• Develop high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, ordering, fairness, and performance-sensitive traffic behavior.
• Partner closely with architecture, RTL, and formal teams to review specifications, close ambiguity early, and improve design debugability and verification completeness before issues harden late in the cycle.
• Drive efficient root-cause analysis across specification, RTL, assertions, test content, and verification infrastructure, and push issues to durable closure.
• Apply the right verification method for the problem, including simulation, formal techniques, emulation, and performance-oriented verification where appropriate.
• Influence methodology and infrastructure across the broader horizontal interconnect verification effort, not just the block directly assigned to you.
• Mentor engineers and raise the technical bar through reviews, debug leadership, stronger verification practices, and reusable infrastructure.

Skills

SystemVerilog

CPU/SoC verification

Verification planning

Python scripting

Debugging

Formal verification

Architecture understanding

Mentoring

Education

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science

Tools

Verilog simulation toolchain

Emulation

Performance verification

Job description

SiFive is seeking a Principal Design Verification Engineer in Austin, TX to lead verification strategy for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms.

This principal tech-lead role spans architecture-aware verification, RTL, formal, performance, and design verification teams to ensure correct data movement, protocol correctness, and robust subsystem integration.