FPGA/ASIC SoC Design Engineer

SpaceX; Irvine (CA); On-site; USD 125,000 - 195,000; Full time

Benefits offered by this job

Stock options

Medical, Vision & Dental

401(k)

Paid vacation

Job summary

SpaceX in Irvine is seeking an FPGA/ASIC Design Engineer to develop next‑generation FPGAs and ASICs for Starlink. You will work with cross‑functional teams to design, verify, and optimize complex SoC blocks, using Verilog/SystemVerilog.

The role requires 1+ years RTL experience, proficiency in Python/C++/Bash, and a strong hardware foundation. On‑site position with competitive compensation, benefits, and stock options.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
• 1+ years of RTL design experience using SystemVerilog, Verilog or VHDL.

Responsibilities

• Design ASICs and/or FPGAs for Starlink projects using Verilog/SystemVerilog.
• Optimize designs for power, performance, and area.
• Participate in full design lifecycle from architecture to validation.
• Collaborate with software engineers on production software for designs.

Skills

RTL Design

Python

C/C++

Bash

DSP design

Modem design

PCB debugging

Cross‑functional

Teamwork

Adaptability

Education

Bachelor's degree in EE/CE/CS/Physics

Master's in EE/CE or related

Tools

HDL simulators

SpyGlass

Vivado

Quartus II

Job description

SpaceX in Irvine is seeking an FPGA/ASIC Design Engineer to develop next‑generation FPGAs and ASICs for Starlink. You will work with cross‑functional teams to design, verify, and optimize complex SoC blocks, using Verilog/SystemVerilog.

The role requires 1+ years RTL experience, proficiency in Python/C++/Bash, and a strong hardware foundation. On‑site position with competitive compensation, benefits, and stock options.