Space-Grade ASIC Physical Design Engineer

SpaceX; Austin (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Stock options

Bonus eligibility

401(k)

Health insurance

Dental insurance

Paid time off

Holidays

Parental leave

Job summary

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) to advance next‑generation ASICs for Starlink and space/groud infrastructure. You’ll join cross‑disciplinary teams and contribute to design feasibility, timing, power, and area targets, helping deliver high‑performance connectivity globally.

The role requires hands‑on RTL2GDSII experience, strong EDA tool knowledge, and scripting skills. Expect collaboration across teams, extended hours, and a pathway toward advanced fabrication

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development.

Responsibilities

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Skills

RTL2GDSII flow

EDA tools

FinFET CMOS physics

Digital design basics

Standard cells

CMOS power

DFT/MBIST

Scripting (Python)

Education

Bachelor’s degree in EE/CE/CS

Tools

Virtualization tools

Job description

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) to advance next‑generation ASICs for Starlink and space/groud infrastructure. You’ll join cross‑disciplinary teams and contribute to design feasibility, timing, power, and area targets, helping deliver high‑performance connectivity globally.

The role requires hands‑on RTL2GDSII experience, strong EDA tool knowledge, and scripting skills. Expect collaboration across teams, extended hours, and a pathway toward advanced fabrication