Space-Grade ASIC/FPGA Design Engineer

SpaceX; Palo Alto (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Medical, vision, dental coverage

Paid parental leave

3 weeks paid vacation

10+ paid holidays

Job summary

SpaceX is seeking an ASIC Design Engineer (Silicon Engineering) to develop cutting-edge ASICs and FPGAs for Starlink. You will collaborate with systems, firmware, architecture, and design teams to drive power- and area-optimized SoC solutions for space and ground infrastructure.

The role emphasizes full design lifecycle, from high-level architecture to validation, with opportunities to contribute to back-end integration and software collaboration. A strong hardware foundation is essential.

Qualifications

• Bachelor’s degree required in EE/CE/CS/Physics.
• 1+ year of RTL design experience with SystemVerilog, Verilog, or VHDL.
• Strong foundation in electrical engineering fundamentals.

Responsibilities

• Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/SystemVerilog.
• Optimize designs for power, performance and area.
• Participate in the full ASIC/FPGA design lifecycle from concept to validation with backend teams.
• Build tools to analyze data on orbit and in the lab.
• High-level architectural design for test systems to support validation and interoperability.
• Collaborate with software engineers in developing production software for designs.

Skills

RTL Design

SystemVerilog

Verilog

VHDL

Python

C/C++

Bash

AXI/APB protocols

EDA tools

Lab debugging

Team collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics

Master’s in Electrical/Computer Engineering or related field

Tools

HDL simulators (VCS/Questa/IES)

HDL Lint (Spyglass)

Xilinx Vivado

Quartus II

Job description

SpaceX is seeking an ASIC Design Engineer (Silicon Engineering) to develop cutting-edge ASICs and FPGAs for Starlink. You will collaborate with systems, firmware, architecture, and design teams to drive power- and area-optimized SoC solutions for space and ground infrastructure.

The role emphasizes full design lifecycle, from high-level architecture to validation, with opportunities to contribute to back-end integration and software collaboration. A strong hardware foundation is essential.