SoC Verification Engineer (RISC-V, IP & Tooling)

Inspire Semiconductor, Inc.; Austin (TX); Hybrid; USD 130,000 - 185,000; Full time

Job summary

InspireSemi is seeking a SoC Design Verification Engineer to verify a high-performance SoC with RISC-V core, interconnect, and peripheral IPs. You will develop verification plans, build testbenches, and ensure design quality before tape-out.

The role requires 5+ years in ASIC/SoC verification, expertise in SystemVerilog/UVM, and strong scripting. Collaboration with RTL and software teams is essential. Hybrid work in Austin with strong compensation and equity.

Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering or related field.
• 5+ years of hands-on ASIC/SoC design verification experience.
• Strong proficiency in SystemVerilog, UVM, and simulation tools (e.g., Xcelium).
• Solid understanding of digital design fundamentals, RTL design, and synthesis flow.
• Experience with functional coverage, assertions, and scoreboarding.
• Strong scripting and programming skills (Python, Perl, TCL, C/C++).
• Knowledge of common bus protocols (AXI, AHB, PCIe, DDR4/5, etc.).
• Working knowledge of version control and CI tools (Git, Jenkins, Jira, Confluence).
• Solid debugging skills, analytical thinking, and attention to detail.

Responsibilities

• Develop and execute verification plans for complex SoC digital designs.
• Create and maintain UVM/SystemVerilog based testbenches and environments.
• Write, debug, and execute constrained-random and directed test cases.
• Implement RISC-V ISA compliance tests.
• Perform functional coverage analysis and close coverage gaps.
• Run regressions, analyze failures, and drive bug closure.
• Connect simulations to real user interfaces, stimulus generators, and checkers.
• Collaborate with RTL design engineers, architects, and software teams.
• Contribute to verification methodologies and automation scripts.

Job description

InspireSemi is seeking a SoC Design Verification Engineer to verify a high-performance SoC with RISC-V core, interconnect, and peripheral IPs. You will develop verification plans, build testbenches, and ensure design quality before tape-out.

The role requires 5+ years in ASIC/SoC verification, expertise in SystemVerilog/UVM, and strong scripting. Collaboration with RTL and software teams is essential. Hybrid work in Austin with strong compensation and equity.