SoC Design Verification Engineer – Performance & Silicon

Etched; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 monthly credit for waiving medical benefits

Wellness benefits for fitness and mental health

Daily lunch and dinner in the office

Job summary

Etched is looking for a Design Verification Engineer to join the Systems/Performance Verification team in Austin, Texas. The ideal candidate will ensure custom IPs are robust, high-performance, and silicon-ready, working alongside architects and developers. Responsibilities include verifying design performance, tuning software for efficiency, and developing tests in SystemVerilog and Python. Benefits include medical packages and daily meals in the office. Regular collaboration with teams in San Jose expected.

Qualifications

• Strong understanding of digital design, RTL, and ASIC design flows.
• Hands-on experience with performance verification and modeling.
• Comfortable developing checkers and testbenches in SystemVerilog.
• Skilled in writing Python scripts for automation and performance analysis.
• Experience building and maintaining performance models for chip subsystems.

Responsibilities

• Verify the performance features of the design with architects and RTL designers.
• Identify performance bottlenecks with software developers.
• Develop test plans and infrastructure/tools for verification.
• Analyze coverage to ensure all performance features are covered.
• Conduct performance tuning and debug issues on silicon.

Skills

Digital design knowledge

Performance verification experience

SystemVerilog proficiency

Python scripting skills

Modeling chip subsystems

Understanding of memory hierarchies

Kernel level performance metrics

Performance bottleneck analysis

Job description

Etched is looking for a Design Verification Engineer to join the Systems/Performance Verification team in Austin, Texas. The ideal candidate will ensure custom IPs are robust, high-performance, and silicon-ready, working alongside architects and developers. Responsibilities include verifying design performance, tuning software for efficiency, and developing tests in SystemVerilog and Python. Benefits include medical packages and daily meals in the office. Regular collaboration with teams in San Jose expected.