SoC Design Verification Engineer

Inspire Semiconductor; Austin (TX); Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

Equity

Hybrid work in Austin

Remote work considered for exceptional

Job summary

Inspire Semiconductor seeks a skilled SoC Design Verification Engineer to verify complex ASIC/SoC designs, focusing on the RISC-V core, network, and IP integrations. You will develop verification plans, build UVM-based testbenches, and ensure functional correctness before tape-out.

The role requires 5+ years of hands-on verification, strong SystemVerilog/UVM knowledge, and experience with regression, coverage, and scripting.

Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering (or related field).
• 5+ years hands-on experience in ASIC/SoC design verification.
• Strong proficiency in SystemVerilog, UVM, and simulation tools (e.g., Xcelium).
• Solid understanding of digital design fundamentals, RTL design, and synthesis flow.
• Experience with functional coverage, assertions, and scoreboarding.
• Scripting/programming skills (Python, Perl, TCL, C/C++).
• Knowledge of common bus protocols (AXI, AHB, PCIe, DDR4/5).
• Version control and CI tools (Git, Jenkins, Jira, Confluence).
• Strong debugging skills, analytical thinking, and attention to detail.

Responsibilities

• Develop and execute verification plans for complex SoC digital designs.
• Create and maintain UVM/SystemVerilog-based testbenches and environments.
• Write, debug, and execute constrained-random and directed test cases.
• Implement RISC-V ISA compliance tests.
• Perform functional coverage analysis and close coverage gaps.
• Perform regression runs, analyze failures, and drive bug closure.
• Connect simulations to real user interfaces, stimulus generators, and checkers.
• Collaborate with RTL, architecture, and software teams.
• Contribute to verification methodologies and automation scripts.
• Perform preliminary debug of discovered issues.

Skills

SystemVerilog

UVM

Constrained-random

Directed test cases

Python

Debugging

Regression testing

RTL design understanding

Education

Bachelor's or Master's in Electrical/ Electronics/ Computer Engineering

Tools

Xcelium

Cadence EDA tools

Zebu

Palladium

Verdi

Job description

About Us:

AtInspireSemi,we'renot just building a chip;we'rerevolutionizing high-performance computing. Our groundbreaking architecture packsthousands of 64-bit CPU coresonto a single chip, all tightly integrated with a high-performance interconnect.We'redriven by a mission to make high-performance computing moreaccessible and energy-efficient, with a developer-friendly programming model. Ready to make a real impact? Join our passionate team!

Why JoinInspireSemi?

• Make an Impact:Your work will directly contribute to building a high-performancecomputeaccelerator for scientific, AI, and other applications.
• Rewarding Compensation:We offercompetitive salaries, benefits, and equity.
• Flexibility:Benefit from ahybrid work environmentin our Austin offices, with exceptional candidates considered forfully remotework.
• Grow With Us:Contribute to the development and improvement of verification methodologies, tools, and automation scripts.

The Opportunity:

We are looking for aSoC Design Verification Engineertosupportthe complete verification of our innovative System-on-Chip (SoC). This critical role encompasses ourRISC-V core, network, and 3rd-party peripheral IP integrations. You willbe responsible fordeveloping comprehensive verification plans, building testbenches, and ensuring the highest level of design quality and functional correctness before tape-out.

What You'll Do:

• Develop and executeverification plansfor complex SoC digital designs.
• Create and maintainUVM/SystemVerilogbased testbenchesand environments.
• Write, debug, and executeconstrained-randomand directed test cases.
• ImplementRISC-V ISA compliance tests.
• Perform functional coverage analysis andclose coverage gaps.
• Perform regression runs,analyze failures, and drive bug closure.
• Connect simulations to real user interfaces, stimulus generators, and checkers.
• Collaborate closely with RTL design engineers, architects, and software teams.
• Contribute to the development and improvement of verification methodologies and automation scripts.
• Perform preliminary debug of discovered issues.

What You Bring:

• ABachelor's orMaster's degreein Electrical, Electronics, or Computer Engineering (or related field).
• 5+ yearsof hands-on experience in ASIC/SoC design verification.
• StrongproficiencyinSystemVerilog, UVM, and simulation tools (e.g.,Xcelium).
• Solid understandingofdigital design fundamentals, RTL design, and synthesis flow.
• Experience withfunctional coverage, assertions, andscoreboarding.
• Strongscripting and programming skills(Python, Perl, TCL, C/C++).
• Knowledge of common bus protocols (AXI, AHB, PCIe, DDR4/5, etc.).
• Working knowledge of version control and continuous integration tools (e.g.,Git, Jenkins, Jira, andConfluence).
• Solid debugging skills, analytical thinking, and attention to detail.

Bonus Points:

• Experience withFormalverification(Conformal LEC).
• Hands-on experience withemulation systems(Zebu, Palladium) orFPGA prototypes.
• Experience withCadence EDA tools.

Ifyou'reexcited about pushing the boundaries of computing and working on truly innovative technology in a rewarding environment,we'dlove to hear from you!