Design Verification Lead

JDWK; Austin (TX); Hybrid; USD 140,000 - 230,000; Full time

Benefits offered by this job

Ownership of verification strategy

Remote-friendly startup

Job summary

JDWK Inc. is building a fast-moving hardware team focused on RISC-V based SoCs. We seek a Design Verification Engineer to own the verification environment and drive scalable testbench automation across RTL and firmware layers.

You will develop constrained-random and coverage-driven tests, integrate CI/CD, and collaborate with RTL, FPGA, and software teams to ensure comprehensive system-level verification across simulation and prototyping platforms.

Qualifications

• 5+ years of experience in ASIC/SoC design verification.
• Strong proficiency in SystemVerilog/UVM or equivalent.
• Hands-on experience verifying RISC-V cores, memory subsystems, and interconnects.
• Experience developing regression and CI flows (Jenkins, GitLab CI).
• Proficiency in scripting (Python, Tcl, shell).
• Knowledge of FPGA-based verification and bring-up.
• Understanding of software-based validation (firmware/bare-metal).
• Strong analytical and debugging skills; startup-friendly.

Responsibilities

• Own the verification environment for the RISC‑V CPU and SoC, from architecture to execution.
• Develop and maintain testbench infrastructure for block and SoC verification.
• Design constrained-random, directed, and coverage-driven tests.
• Integrate verification flows into CI/CD pipelines for regression testing.
• Collaborate with design engineers to implement checkers and assertions.
• Monitor verification coverage metrics and drive closure.
• Leverage FPGA prototyping for accelerated testing and validation.
• Collaborate with software and systems teams to develop test firmware.

Skills

SystemVerilog/UVM

RISC-V verification

CI/CD automation

Python scripting

Debugging

Tools

VCS

Xcelium

Questa

Verilator

QEMU

Job description

JDWK Inc. Design Verification Lead Austin, TX·Remote·Full time Company website

Create, execute, and maintain a design verification environment for the development of a RISC-V based SoC

About JDWK Inc.

JDWK was started with the goal of drastically reducing the time and resources needed to design modern VLSI systems through intelligent and highly configurable automation. We work with customers from concept to tapeout to deliver perfect silicon at a fraction of the cost of traditional design services, while continually enhancing and evolving our software to optimize execution.

Description

About Us

We’re a small, fast-moving team developing RISC-V–based SoCs and the software infrastructure to automate chip design. Our goal is to make advanced silicon development faster, smarter, and more accessible.

We’re looking for a Design Verification Engineer who can take ownership of the verification environment for our SoC and RISC-V CPU core. You’ll be responsible for building a scalable, automated verification framework that continuously validates RTL quality as the design evolves — enabling confident, autonomous design iteration.

This is a high-impact, hands-on role at the center of our hardware development flow.

Role Overview

As the Design Verification Engineer, you’ll architect, implement, and maintain the SoC-level and CPU-level verification environment. You will develop the testbench infrastructure, write test scenarios and coverage models, and integrate regression and continuous verification into our CI flow.

You’ll work closely with RTL designers, FPGA engineers, and software developers to ensure the entire hardware-software stack is verified at both the simulation and system levels.

Key Responsibilities

• Own the verification environment for the RISC-V CPU and SoC, from architecture to execution.
• Develop and maintain UVM/SystemVerilog or equivalent testbench infrastructure for block-level and SoC-level verification.
• Design constrained-random, directed, and coverage-driven tests to validate functional correctness, performance, and corner cases.
• Integrate verification flows into CI/CD pipelines for automated and continuous regression testing.
• Collaborate with design engineers to identify test requirements, implement checkers, and add assertions.
• Monitor verification coverage metrics and drive closure.
• Leverage FPGA prototyping for accelerated testing, firmware validation, and hardware/software co-verification.
• Collaborate with software and systems teams to develop test firmware, diagnostic tools, and bring‑up tests.
• Document methodologies and help establish best practices for verification automation and infrastructure.

Requirements

• 5+ years of experience in ASIC/SoC design verification, including at least one full project cycle from environment bring‑up to tapeout.
• Strong proficiency in SystemVerilog/UVM or equivalent methodologies for testbench development.
• Hands‑on experience verifying RISC‑V or other CPU cores, memory subsystems, and on‑chip interconnects.
• Proficiency with simulation, coverage, and debugging tools (e.g., VCS, Xcelium, Questa).
• Experience developing and managing regression and CI flows (Jenkins, GitLab CI, or similar).
• Ability to script and automate using Python, Tcl, or shell scripting.
• Knowledge of FPGA-based verification and bring‑up.
• Understanding of software‑based validation (e.g., running firmware or bare‑metal tests on emulation or FPGA).
• Strong analytical and debugging skills, with attention to detail and a proactive mindset.
• Comfort working in a startup environment, handling multiple responsibilities and evolving priorities.

Preferred Qualifications

• Familiarity with RISC-V architecture and open-source cores (Rocket, CVA6, Ibex, etc.).
• Experience with formal verification tools and property checking.
• Exposure to co-simulation or virtual platform environments (e.g., Verilator + QEMU).
• Understanding of hardware/software interface verification, including interrupt, DMA, and peripheral validation.
• Contributions to open-source verification frameworks or RISC-V community projects.

What We Offer

• The opportunity to own verification strategy and infrastructure for a complete RISC‑V SoC.
• A broad and challenging role at the intersection of hardware, software, and automation.
• High visibility and technical impact in a small, expert team.