Hybrid Lead Front-End Verification Engineer, RISC-V

Tenstorrent; Austin (CA); On-site; USD 100,000 - 500,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Tenstorrent in Austin or Santa Clara is seeking a Design Verification Engineer to contribute to unit-level verification of our RISC-V CPU front end. You will build testbenches, generate stimulus, and develop checkers for complex microarchitectural scenarios.

You should be fluent with SystemVerilog, UVM, and C++, and comfortable collaborating with RTL designers to trace and fix fetch bugs. This role is hybrid and offers a wide exposure to cutting-edge hardware and software integration.

Qualifications

• Verifying CPU front-end blocks with SystemVerilog, UVM, and C++.
• Hands-on testbench development with precise stimulus and checks.
• Collaborative problem solving with RTL designers on fetch bugs.

Responsibilities

• Build and maintain UVM testbenches for instruction fetch units.
• Develop constrained-random and directed tests for fetch paths.
• Create and maintain C++ reference models and predictors.
• Execute verification plans and track coverage.

Skills

Front-End Verification

Unit-Level Verification

SystemVerilog

UVM

C++

Tools

Verilator

C++ Integration

Job description

Tenstorrent in Austin or Santa Clara is seeking a Design Verification Engineer to contribute to unit-level verification of our RISC-V CPU front end. You will build testbenches, generate stimulus, and develop checkers for complex microarchitectural scenarios.

You should be fluent with SystemVerilog, UVM, and C++, and comfortable collaborating with RTL designers to trace and fix fetch bugs. This role is hybrid and offers a wide exposure to cutting-edge hardware and software integration.