Remote Senior Verification Engineer — ASIC/SoC

Ipro Networks Pte. Ltd.; United States; Remote; USD 152,000 - 179,000; Full time

Job summary

IntelliPro seeks a Sr. Verification Engineer to join our ASIC & Networking efforts on a remote basis, with relocation options to Southern California or Austin, TX if converted.

The role covers IP, subsystem, and full SoC verification, leveraging constrained-random, formal methods, and AI-assisted stimulus generation. You will own verification planning, develop environments and scoreboards, and mentor junior engineers while contributing to a tapeout target in 2027.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or 7+ years equivalent experience.
• Minimum five years of professional experience in ASIC or SoC functional verification.
• Hands-on expertise in SystemVerilog, UVM or formal testbench development and maintenance.
• Experience with metric-driven verification for planning, assertions, and functional coverage closure.
• Experience verifying complex digital control and datapath logic, including RTL and system-level debug.

Responsibilities

• Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.
• Translate design specifications into verification strategies, measurable coverage goals, and early identification of high-risk scenarios.
• Select verification methods for each problem, including constrained-random simulation, formal analysis, and directed testing.
• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.
• Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results.
• Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels.
• Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics.
• Review testbench architecture and debug methodology, and mentor junior engineers in verification methodology.

Skills

SystemVerilog

UVM

Formal verification

RTL debugging

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Tools

Verilog simulators

C/Python for test stimulus

Job description

IntelliPro seeks a Sr. Verification Engineer to join our ASIC & Networking efforts on a remote basis, with relocation options to Southern California or Austin, TX if converted.

The role covers IP, subsystem, and full SoC verification, leveraging constrained-random, formal methods, and AI-assisted stimulus generation. You will own verification planning, develop environments and scoreboards, and mentor junior engineers while contributing to a tapeout target in 2027.