Data Center SoC Verification Engineer (SystemVerilog/UVM)

Qualcomm; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks a Design Verification Engineer to join the Data Center SoC Verification team. You will verify next‑generation Data Center SoCs powering AI, HPC, and cloud infrastructure.

You will develop scalable verification environments, drive verification closure, and ensure first-silicon success for complex designs, including CPUs, memory subsystems, interconnects, and high‑speed interfaces.

Qualifications

• Bachelor's or master's degree in electrical engineering, Computer Engineering, Computer Science, or related field.
• Minimum 2+ years of design verification experience; senior roles for proven experts.

Responsibilities

• Develop verification plans for SoC, subsystem, and IP features.
• Design System Verilog/UVM-based verification environments.
• Create directed and constrained-random test scenarios.
• Develop assertions, coverage models, and checkers.
• Debug RTL/testbench issues and drive defect resolution.
• Drive coverage closure using functional and code coverage metrics.
• Participate in architecture/design reviews to embed verification requirements early.
• Verify multi-core CPU systems, cache coherency, DDR/HBM memory, PCIe/CXL/Ethernet, security, RAS, power management.

Skills

SystemVerilog

UVM

C

SVA

CDV

System use cases

Python

Education

Electrical Engineering

Computer Engineering

Computer Science

Tools

Veloce

Palladium

ZeBu

Job description

Qualcomm Technologies, Inc. seeks a Design Verification Engineer to join the Data Center SoC Verification team. You will verify next‑generation Data Center SoCs powering AI, HPC, and cloud infrastructure.

You will develop scalable verification environments, drive verification closure, and ensure first-silicon success for complex designs, including CPUs, memory subsystems, interconnects, and high‑speed interfaces.