Staff SoC Verification Architect

Efficient Computer; San Francisco, Pittsburgh, Austin (CA, Allegheny County, TX); On-site; USD 160,000 - 245,000; Full time

Benefits offered by this job

401(k) match

Company-paid benefits

Paid parental leave

Flexibility to grow your skills

Equity share

Job summary

Efficient Computer in San Francisco is seeking an experienced Staff Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team.

This role offers ownership of verification challenges, exposure to edge and data center scale, and collaboration with software teams pre-silicon; a strong background in UVM, SystemVerilog, Python, and C/C++ is required, with 10+ years of experience.

Qualifications

• Bachelor's or Master's/PhD in Electrical/Computer Engineering or related field.
• 10+ years of ASIC/SoC design verification experience with multiple full cycles from testbench to tapeout.
• Expertise in UVM-based testbench architecture and constrained-random verification.
• C/C++ for modelling or verification.
• Proven track record of driving functional and code coverage to tapeout sign-off.
• Ability to debug complex simulation failures.
• Proficiency in Python for test automation, log analysis, and regression flow.
• Strong communication of verification risk, status and tradeoffs.

Responsibilities

• Drive functional verification of complex SoC/IP designs from spec to tapeout.
• Own testbench architecture and coverage closure for multi-million-gate designs.
• Debug complex simulation failures and optimize verification flows.
• Collaborate with software and hardware teams pre-silicon to de-risk schedules.

Skills

UVM-based testbench

SystemVerilog

C/C++

Python scripting

Debug complex simulations

Communication of risk

Education

Bachelor's or Master's/PhD in Electrical/Computer Engineering

Tools

UVM

SystemVerilog

Python

Job description

Efficient Computer in San Francisco is seeking an experienced Staff Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team.

This role offers ownership of verification challenges, exposure to edge and data center scale, and collaboration with software teams pre-silicon; a strong background in UVM, SystemVerilog, Python, and C/C++ is required, with 10+ years of experience.