SoC STA Design Engineer - Timing Signoff Lead

NXP Semiconductors NV; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

NXP Semiconductors in Austin, TX seeks an experienced SoC STA engineer to own end-to-end timing signoff across complex designs. You will drive constraint creation, validate with frontend, IP, and DFT teams, and collaborate with implementation to close timing at advanced nodes.

The role emphasizes scripting (Python, TCL, Perl) for timing ECOs, AI-assisted automation, and continuous methodology improvements to boost design quality and productivity.

Qualifications

• Bachelor’s or Master’s in Electrical/Electronics Engineering or related field.
• 3–6 years of experience in ASIC/SoC Timing Analysis.
• Strong knowledge of industry STA tools (Synopsys flows).
• Strong communication skills.

Responsibilities

• Own end-to-end Constraints and Timing Signoff.
• Drive Timing Constraints Creation and Validation.
• Validate Constraints with Frontend, IP and DFT teams and resolve timing issues.
• Close Timing with Implementation team and Full Chip STA team.
• Provide timing feedback and develop automated/manual timing fixes.

Skills

Communication skills

STA experience

SoC timing analysis

Python

TCL

Perl

Education

Bachelor’s or Master’s in Electrical/Electronics Engineering or related field

Tools

Synopsys flows

Python

TCL

Perl

Job description

NXP Semiconductors in Austin, TX seeks an experienced SoC STA engineer to own end-to-end timing signoff across complex designs. You will drive constraint creation, validate with frontend, IP, and DFT teams, and collaborate with implementation to close timing at advanced nodes.

The role emphasizes scripting (Python, TCL, Perl) for timing ECOs, AI-assisted automation, and continuous methodology improvements to boost design quality and productivity.