Senior STA Signoff & Timing Methodology Engineer

NVIDIA; Austin (TX); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an innovative Senior STA Signoff Methodology Engineer in Austin, TX. You will drive sign-off strategies for GPUs/CPUs/SoCs, optimize performance, yield, and reliability through advanced modeling, analysis, and automation.

You will collaborate with design and timing teams to deploy sophisticated timing-signoff strategies and develop tools that extend beyond standard EDA capabilities. A strong background in FinFET/CMOS at leading nodes is valued.

Qualifications

• MS in Electrical or Computer Engineering or equivalent experience.
• 8+ years of ASIC design and timing experience.
• Solid understanding of RC extraction, device physics, STA methodologies, and EDA tool limitations.
• Experience with low-power techniques (multi-Vt, clock gating, power gating, DVFS, CDC).
• Familiarity with ASIC tools such as PrimeTime, ICC2, RedHawk, Tempus.

Responsibilities

• Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
• Develop STA and PNR flows addressing aging, self-heating, thermal effects, IR drop, electromigration, and other advanced-node effects.
• Collaborate with technology leads, physical-design and timing engineers to deploy timing-signoff strategies for silicon performance.
• Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond standard EDA tools.
• Work across STA, constraints, timing, and power optimization.
• Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.

Skills

8+ years ASIC design & timing

STA methodologies

Device physics

Power optimization

Clock gating & DVFS

Cross-functional collaboration

Education

MS in Electrical or Computer Engineering

Tools

PrimeTime

ICC2

RedHawk

Tempus

Job description

NVIDIA is seeking an innovative Senior STA Signoff Methodology Engineer in Austin, TX. You will drive sign-off strategies for GPUs/CPUs/SoCs, optimize performance, yield, and reliability through advanced modeling, analysis, and automation.

You will collaborate with design and timing teams to deploy sophisticated timing-signoff strategies and develop tools that extend beyond standard EDA capabilities. A strong background in FinFET/CMOS at leading nodes is valued.