Senior SoC Physical Design Lead | End-to-End Tapeout

NXP Semiconductors NV; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

NXP Semiconductors NV in Austin, TX is seeking an experienced Digital Designer for SoC Implementation / Physical Design to own end-to-end physical design execution from RTL to silicon for advanced semiconductor products. This role demands deep technical expertise to deliver silicon meeting PPA targets.

You will lead floorplanning, synthesis, place & route, and signoff, drive timing and power closure, and collaborate with architecture, RTL, and verification teams.

Qualifications

• Bachelor's or Master's in Electrical / Electronics Engineering or related field.
• 10+ years of experience in ASIC / SoC physical design.
• Strong knowledge of industry EDA tools (Synopsys, Cadence flows).
• Strong communication skills.

Responsibilities

• Own end-to-end physical design execution from RTL to tapeout.
• Lead floorplanning, synthesis, PNR, CTS, routing, STA, and signoff.
• Drive timing, power, IR/EM, and PDN/PDV closure for tapeout readiness.
• Deliver optimized PPA across complex designs.
• Mentor and develop team members; report to senior leadership.
• Collaborate with architecture, RTL, verification, and IP vendors.

Skills

RTL-to-GDSII flow

Floorplanning

Synthesis

Place & Route

STA & Signoff

Physical Verification

Advanced Node 5nm

Low Power UPF/CLP

Scripting Python/TCL/Perl

Education

Bachelor's or Master's in Electrical/Electronics Engineering

Tools

Synopsys

Cadence

Job description

NXP Semiconductors NV in Austin, TX is seeking an experienced Digital Designer for SoC Implementation / Physical Design to own end-to-end physical design execution from RTL to silicon for advanced semiconductor products. This role demands deep technical expertise to deliver silicon meeting PPA targets.

You will lead floorplanning, synthesis, place & route, and signoff, drive timing and power closure, and collaborate with architecture, RTL, and verification teams.